Browse Prior Art Database

BICMOS Metastability Latch

IP.com Disclosure Number: IPCOM000122376D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+2]

Abstract

When a synchronous logic structure receives data from an asynchronous source, read errors can occur due to a phenomenon called metastability. Metastability occurs within a latch whenever the data input changes just when the clock is trying to store the input value. The circuit illustrated in the figure shows a technique where very large storage devices can be used to increase the "feedback" of the storage devices, thus improving the metastability characteristics of the design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 74% of the total text.

BICMOS Metastability Latch

      When a synchronous logic structure receives data from an
asynchronous source, read errors can occur due to a phenomenon called
metastability.  Metastability occurs within a latch whenever the data
input changes just when the clock is trying to store the input value.
The circuit illustrated in the figure shows a technique where very
large storage devices can be used to increase the "feedback" of the
storage devices, thus improving the metastability characteristics of
the design.

      The discussion will restrict itself to the L1 portion of the
latch (devices N0-N19 and P0-P15), although it applies to the L2
portion of the latch as well.  The storage devices P12, P13, N16, and
N17 are very large and give very good metastability performance.  The
bipolar TUP0, TUP3, TDN0, and TDN3 are able to update the latch very
quickly, without loading the internal net.  A single FET inverter is
used to drive the output buffer.

      The latch functions are:  When the clock is active, devices N0-
N15 and P0-P11 activate either bipolars TDN0 and TUP3 or TDN3 and
TUP0, to overdrive the storage inverters. When the latch is inactive,
all bipolar drive devices are deactivated and the state is held by
the storage devices. All signals which act upon the latch are
inverter buffered from the storage nodes, thus reducing the load to
these nets.  The bipolar goes to a high impedance state then the
clock is shut off and has the ability to overdrive...