Browse Prior Art Database

High Performance BICMOS L2 Latch for Level Sensitive Scan Design

IP.com Disclosure Number: IPCOM000122378D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+3]

Abstract

Illustrated in the figure is the schematic of the improved L2 latch design. The L2 storage devices P13, P14, N14, and N15 are small to improve performance when the latch needs to change states. The data port is duplicated to drive both true and complement phases of data into the L2. Each phase drives directly into the output buffers without inverting. Essentially the data port, one of the latch nodes and the output buffer have been combined into one stage block.

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High Performance BICMOS L2 Latch for Level Sensitive Scan Design

      Illustrated in the figure is the schematic of the
improved L2 latch design.  The L2 storage devices P13, P14, N14, and
N15 are small to improve performance when the latch needs to change
states.  The data port is duplicated to drive both true and
complement phases of data into the L2.  Each phase drives directly
into the output buffers without inverting. Essentially the data port,
one of the latch nodes and the output buffer have been combined into
one stage block.

      The latch functions as follows:  When the clock is activated,
true and complement data is forced onto the latch nodes by devices
P9-P12 and N10-N13.  These nodes also provide the drive to the output
bipolars, devices TUP1 and TUP2, which in turn drive the logic loads.
In parallel, the L1 data and the B clock drive the buffer pull-down
devices N16, N17, N21, and N22.  Essentially, the performance for the
L1 data to the L2 outputs is the same as a 2-way AND book.  When
the clock is deactivated, the L2 inverters, devices P13, P14, N14,
and N15 retain the state of the latch and the level of the outputs.

      Analysis of this latch configuration shows a significant
improvement in L2 performance.