Browse Prior Art Database

Shorts Protected ECL Driver with Disable

IP.com Disclosure Number: IPCOM000122382D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Braden, JJ: AUTHOR [+5]

Abstract

This circuit converts a single-ended input from CMOS to differential high speed ECL off-chip driver output. This circuit also has short- circuit protection and can be disabled when not in use.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Shorts Protected ECL Driver with Disable

      This circuit converts a single-ended input from CMOS to
differential high speed ECL off-chip driver output.  This circuit
also has short- circuit protection and can be disabled when not in
use.

      The figure is a schematic of this driver.  When the +disable
input is high, the driver is disabled.  When disabled, NET10 is also
high, which causes NFET T3 to pull NET7 down.  This keeps transistors
Q0 and Q1 off.  An up level at NET10 prevents base current from going
into the output emitter followers Q3 and Q2 because PFETs TP8 and TP9
disconnect their bases.  PFET current sources TP4 and TP0 are off
because of the up level on their gates.  There is essentially no
current flow anywhere in the driver circuit when it is disabled, only
leakage current.

      The driver is activated by placing a low level on the +disable
input.  This causes a low level on NET10, which turns off NFET T3,
allowing the bias circuit connected to NET7 to function.  Also, this
down level activates PFET current sources TP4 and TP0 and NFET
current sources T11 and T12.  NFETs T11 and T12 pull the gates of
PFET switches TP8 and TP9 down which activate the output transistors
Q3 and Q2 by supplying base drive.  Also, the down level on NET10
activates PFET current sources TP4 and TP0.  This causes the single
end to the differential converter and the bias circuit to function.

      When an input signal is applied to the input, a true signal is
at NET4 and the inverted signal is at NET8, producing a differential
signal across the differential pair formed by NPNs Q0 and Q1.  The
physical dimensions of NFETs T2 and T0 are such that they sink equal
currents to PFET current sources TP4 and TP0.  When the input is such
that T2 is on, it sinks a current equal to that of the current source
T...