Browse Prior Art Database

ADC Autozero and Input Centering Scheme for High Noise Environment

IP.com Disclosure Number: IPCOM000122384D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 164K

Publishing Venue

IBM

Related People

Braden, JJ: AUTHOR [+6]

Abstract

Disclosed is a method to subtract unwanted DC offsets from the input of an analog-to-digital converter (ADC) by using a digitally controlled current source which nulls out and recenters the analog input signal.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

ADC Autozero and Input Centering Scheme for High Noise Environment

      Disclosed is a method to subtract unwanted DC offsets
from the input of an analog-to-digital converter (ADC) by using a
digitally controlled current source which nulls out and recenters the
analog input signal.

      Fig. 1 shows the topology for the 6-bit Flash ADC.  It contains
the resistor ladder and 63 comparators that tap off the ladder at 63
discrete voltage reference points between the top (TOPREF) and bottom
(BOTREF) references.  The output of a low-pass filter (FILTOUT) is
emitter followed by Q1 whose bias current is provided by resistor
REXT2.  The emitter follower Q1 then drives capacitor CEXT1 and
resistor REXT1 which together AC couple the input signal to the
middle of the ladder (MID).  External capacitors CEXT2 and CEXT3
provide a low impedence path to prevent AC signal currents from being
driven into the ADC resistor ladder. The Encoder converts the 63
latched comparator outputs to a 6-bit digital code.  The code
assignment is such that the middle of the ladder corresponds to a
zero input signal; therefore, the zero code lies between 011111 and
100000. NUL1 is a DC current source that nominally nulls out the
input bias current of the 63 comparators connected to the ADIN pin.
Therefore, under nominal conditions without the presence of noise
when the ADIN signal is zero, the ADC output would toggle between
011111 and 100000.

      However, in the presence of noise, the zero code of the ADC may
not be between 011111 and 100000 and a DC Restore DAC (DCRDAC) is
needed.  The DCRDAC is a bidirectional current output 5-bit digital-
to-analog converter (DAC) which drives current into resistor REXT1 to
move the baseline of ADIN above or below MID.  This allows for the
ADIN to be incrementally stepped so as to give a zero code at the ADC
output with zero signal.  Resistor REXT3 along with VREF, a 2.25 volt
reference, set the least significant bit (LSB) current of the DCRDAC.
In the DCRDAC a DC current source of value 16 LSBs is dotted with a
current-sinking 5-bit DAC.  Therefore, the output of the DCRDAC is
from -15 to +16 LSBs, where positive current goes into REXT1 and
drives ADIN up with respect to MID.  The value of the DCRDAC LSB
current is such that, when dropped across REXT1, it is 4 mV or 1/4 of
an ADC LSB.  This makes the overall correction range of the DCRDAC
from +4.00 to -3.75 ADC LSBs with an incremental stepsize 1/4 ADC
LSB.

      A simplified schematic of the DCRDAC is shown in Fig. 2.  The
VREF input is resistor divided down by R1 and R4 so that a voltage of
VREF/7 appears at the +input to the OpAmp. The OpAmp maintains a
constant current of VREF/(7*REXT3) through PFETs TP2-TP7.  PFETs
TP0/1 and TP8/9 divide this current by 3 so that the current in PFETs
TP0/1 and TP8/9 is VREF/(21*REXT3).  The DCRDAC LSB is set by
dividing the current of TP0/1 by 16 in the NFET current divider
formed by T0/1 (repeated 16 times) and...