Browse Prior Art Database

Dynamic Pipelined Skip Stage Unit

IP.com Disclosure Number: IPCOM000122392D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Handlogten, GH: AUTHOR

Abstract

A method to reduce the latency associated with a pipeline is disclosed. When every stage of a pipeline is not filled, it is possible to remove a cycle from the amount of time required to produce a result. This is accomplished by allowing an operation to proceed into the subsequent stage if that stage is vacant.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dynamic Pipelined Skip Stage Unit

      A method to reduce the latency associated with a pipeline
is disclosed.  When every stage of a pipeline is not filled, it is
possible to remove a cycle from the amount of time required to
produce a result.  This is accomplished by allowing an operation to
proceed into the subsequent stage if that stage is vacant.

      There are fixed costs associated with pipelining, leaving each
stage with less than the cycle time to accomplish its function.  This
pipelining overhead falls into five categories.  They are:  clock
skew, latch setup and delay, critical paths feeding non-critical
paths, selection of convenient latch points, and remaining unused
time being less than the delay through the required logic gate.

      Whenever possible, as much of the overhead as practical will be
removed by this invention.  This is accomplished by causing the data
to circumvent the latches that partition the pipeline stages.

      Pipelined units are designed to be capable of accepting new
operations every cycle.  But this, of course, does not always happen.
When an operation is sent to the unit, if the succeeding stage is
vacant, progress does not have to stop at the partitioning register.
The register can be bypassed and some progress can be made into that
succeeding (vacant) stage.  Over several stages in the pipeline, the
progress accumulates to the point where the final result is obtained
one cycle early.  Basically, one operation is allowed to flush
through the unit, while operations ahead and behind can continue to
be pipelined.  If operations are sent to the unit every other cycle
or less, the unit will be continuously bypassing the latches, and all
results will be obtained a cycle early.  However, operations that use
iterative algorithms that loop through some stages cannot bypass to
vacant stages and also must prevent following instructions from
attempting to do so. An example of this may be divide and square
root.

      Bypassing the registers may be accompli...