Browse Prior Art Database

High Performance Multiplexed Bus Structure

IP.com Disclosure Number: IPCOM000122410D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 172K

Publishing Venue

IBM

Related People

Azevedo, M: AUTHOR [+5]

Abstract

Disclosed is a common bus structure for achieving a high level of connectivity among a group of data transfer components. The bus structure maximizes the data rate capability by employing a data streaming method of response interlocking whereby the response to a soliciting request need not be required to occur during the service time of issue. Accompanying the bus structure is a protocol which supports the transfer of both data and control quantities.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

High Performance Multiplexed Bus Structure

      Disclosed is a common bus structure for achieving a high
level of connectivity among a group of data transfer components.  The
bus structure maximizes the data rate capability by employing a data
streaming method of response interlocking whereby the response to a
soliciting request need not be required to occur during the service
time of issue.  Accompanying the bus structure is a protocol which
supports the transfer of both data and control quantities.

      The bus structure provides a common interface to which all data
transfer components in a system are attached. Since a path must be
established between any such components, the bus employs a method of
time-multiplexing bus ownership to satisfy the underlying requirement
for full connectivity.  The time-multiplex duration, or "service
time" Ts (in seconds) together with the data transfer unit of two
bytes establishes the total bandwidth capability of the bus at 2/Ts
bytes/ sec.

      The ownership of the bus "service time" or "slot" is assigned
dynamically based on the requirements of the Data Transfer Mechanisms
(DTMs) within the components themselves. The bus slot ownership is
assigned utilizing a method of centralized arbitration.  The
arbitration control algorithm which is defined for the application
assures that the "bus slot" allocation satisfies the instantaneous
data rate demands of the components and optimizes data transfer
throughput of the subsystem.

      As illustrated in Fig. 1, communication on the bus is always
conducted between a Master Adapter and a Slave Adapter.  Within any
component may reside one or both adapter types.

      The Master Adapter acts as the initiator of all bus
transactions.  Under the direction of associated DTMs, the Master
Adapters issue requests for bus ownership and pace the requests for,
and the trans mission of, information across the bus.  The Slave
Adapters act as responders to operations initiated by the Master
Adapter.  The Slave Adapter may communicate on the bus only when the
bus has been acquired by the Master Adapter to which it is
associated.

      The Bus Adapter forms a common structure which is employed by
each of the components attached to the bus.  The signal definition
and timing at the interface requires strict adherence to standards in
order to ensure optimum compatibility between components.
BUS TOPOLOGY

      The bus employs a 19-wire interface and a simplex line pair
between each Master component and a line out for each Slave Adapter
which connects to the bus.  The bus time-multiplexes usage to share
ownership and establish paths between the components attached to the
bus.  The basic time-multiplex unit or "bus slot" has a fixed
duration which is established based on the performance capabilities
of the technology.  During each data transfer slot, a two-byte data
unit may be transferred between assigned components on the bus.

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