Co-processor for Hardware Supported Measurement and Monitoring Func tions
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
This article describes a co-processor which will ensure the ability to measure and monitor a processor family through many generations of implementations.
Co-processor for Hardware Supported Measurement and
describes a co-processor which will ensure
the ability to measure and monitor a processor family through many
generations of implementations.
conducted on computer systems in both the
laboratory and at customer installations. The purpose of these
measurements is to evaluate the performance of the systems and to
study their behavior in the different operational environments. Many
of these measurements are made by connecting external hardware
monitors to selected signals on the systems under test. However, as
system implementations tend toward very large-scale integration
(VLSI) technology, many of these signals will become inaccessible.
This may make it impossible for many of the hardware measurements,
presently conducted, to be performed in the future. Therefore, in
order to continue to evaluate and measure future generations of
VLSI-based systems, the hardware measurement and performance
monitoring capabilities must be directly architected into the
Fig. 1 is a
functional block diagram illustrating the proposal
of a hardware co-processor to support measurement and monitoring in
an Intel 80386-based system.
and monitoring co-processor (MMCP) unit is
similar to other co-processors in that the MMCP can be viewed as a
unit which is connected to the 80386 via the processor bus. The MMCP
is intended to be used as the collection/event reporting center where
performance information is directly loaded and actively maintained
via a software monitor program which is executed in the 80386
processor as part of a system supervisory program.
As seen in
Fig. 1, the MMCP interfaces directly to the
processor bus. No new interfaces or control signals need to be
defined. The MMCP is similar to the Intel 80387 in the way it is
interfaced to the 80386 system. The new architecture is intended to
expand on the current architecture and extend the functional
capabilities of an 80386- based system to include hardware support of
software event monitoring and program module tracing. Fig. 2 shows
the logical internal design of the proposed MMCP.
The A2, A31
and A30 signals from the 80386 allow the MMCP to
identify which bus cycles are intended for the MMCP. The MMCP
responds only to I/O cycles when bit 31 of the I/O address is zero
and bit 30 of the I/O address is set. The MMCP acts as an I/O
device in a reserved I/O address space similar to the 80387.
and A30 are used to select the MMCP for data
transfers, it is not possible for a program running on the 80386 to
address the MMCP with an I/O instruction. ONLY ESC instructions
cause the 80386 to communicate with the MMCP. The MMCP is capable of
generating an interrupt when a specified event occurs. The MMCP uses
the interrupt (INTR) signal of the processor bus to signal an