Browse Prior Art Database

Multiple Read and Exclusive Write State in MP Caches

IP.com Disclosure Number: IPCOM000122429D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 148K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Disclosed is a new state MREW (multiple read and exclusive write) for MP cache lines. With this provision, a CPU may store into a line in its cache while copies of the line can be concurrently read at other CPU caches. The benefit is increased concurrency of cache reads and writes in MP without changing the architectural rules for coherence.

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Multiple Read and Exclusive Write State in MP Caches

      Disclosed is a new state MREW (multiple read and
exclusive write) for MP cache lines.  With this provision, a CPU may
store into a line in its cache while copies of the line can be
concurrently read at other CPU caches.  The benefit is increased
concurrency of cache reads and writes in MP without changing the
architectural rules for coherence.

      EX (EXclusive) state for cache lines has been employed in MP
designs (e.g., IBM/3090*) for control of cache coherence.  The major
benefit of using EX state is the avoidance of constant store
synchronizations through a central storage controller (e.g., in
IBM/3033).  In typical MP designs a cache line with RO (Read-Only)
state may be read from at multiple CPUs, while a CPU may store into
its cache only when it owns EX state for the associated line. When a
CPU owns EX state on a cache line, it is guaranteed that all remote
copies of the line are invalidated.  When an EX line at a cache is
accessed remotely, proper cross-interrogate (XI) actions are needed
to cause the release of the EX ownership first.  In a more
sophisticated MP design (e.g., IBM/ 3090) it was found beneficial for
a cache line to acquire EX state even when the access is not for
operand store.  For example, when a CPU operand fetch misses in its
cache and when none of the other caches has a copy of the line, it
is often desirable to have the missed line fetched (e.g., from main
storage) with EX state.  Such EX state will be beneficial when the
line is subsequently stored into by the same CPU in close time
neighborhood.  It will however be disadvantageous if the line is
accessed by a remote CPU before it gets stored into locally.
Basic Idea of the Invention

      The major purpose of EX status is to provide observable
serializability of memory modifications (e.g., in IBM/370
architecture).  We observe that such serializability of memory stores
can be properly achieved with states less restricted than
conventional EX state.  We introduce new states to allow a cache line
to be stored into while read from other CPUs concurrently.

      Consider a MP system with a store-through LI cache for each
CPU.  A central storage controller (SC) is employed to resolve
storage accesses that cannot be resolved at individual LI caches.  SC
itself may manage a second level cache (L2).  At a LI directory, each
(valid) line entry can be in one of the following states:  RO
(Read-Only), LRRW (Local Read & Remote Write), MREW (Multiple Read &
Exclusive Write), and EX (EXclusive).  RO and EX states are similar
to conventional ones.  LRRW state may be viewed as RO state with the
extra condition that the line can be in MREW state at a remote cache.
MREW state means that the line can be read from and stored into
locally, while at the same time it can also be ready from remotely.
Each cache line can be MREW in at most one L1 cache at any moment.
We also make the assum...