Browse Prior Art Database

Improved Testability in DCS Circuits

IP.com Disclosure Number: IPCOM000122433D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Adams, RL: AUTHOR

Abstract

This article describes a method, using Differential Current Switch (DCS)-type circuits, to inject additional LSSD stuck-fault patterns utilizing unused inputs to existing DCS circuits. This method injects the additional patterns without adding an additional level of logic in critical timing paths. This method can be used to improve the testability for both deterministic chip test patterns and pseudo-random TCM self-test patterns.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 86% of the total text.

Improved Testability in DCS Circuits

      This article describes a method, using Differential
Current Switch (DCS)-type circuits, to inject additional LSSD
stuck-fault patterns utilizing unused inputs to existing DCS
circuits.  This method injects the additional patterns without adding
an additional level of logic in critical timing paths.  This method
can be used to improve the testability for both deterministic chip
test patterns and pseudo-random TCM self-test patterns.

      Logic chips that mount on Thermal Controlled Modules (TCMs)
which are tested using pseudo-random self-test patterns require that
all such chips are testable with random patterns.  This is a more
stringent requirement than the testability with deterministic
patterns required by chip manufacturing.  It often requires that
additional patterns be injected using fixed value scan only Shift
Register Latches (SRLs) to contain the pattern and an Exclusive OR
circuit to add in the pattern to the logic path.  The added Exclusive
OR circuit frequently introduces an extra level of logic in a
critical timing path.  This article describes a method of injecting
the pattern without adding an extra level of logic.  It can only be
implemented in chips that use DCS technology.

      DCS logic circuits are built using a selector circuit as the
basic circuit building block, unlike most other technologies that use
an OR circuit as the basic building block.  See Fig. 1 for an example
of the way DCS...