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Browse Prior Art Database

Two Way Interleaving with Page Mode for Packet Mode Accesses

IP.com Disclosure Number: IPCOM000122436D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 134K

Publishing Venue

IBM

Related People

Ozaki, B: AUTHOR [+2]

Abstract

Described is a two-way interleaving method with page mode for packet mode accesses which is designed to increase the efficiency of information transfer between a memory controller and a processor while utilizing available bandwidth.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

Two Way Interleaving with Page Mode for Packet Mode Accesses

      Described is a two-way interleaving method with page mode
for packet mode accesses which is designed to increase the efficiency
of information transfer between a memory controller and a processor
while utilizing available bandwidth.

      Generally, the use of packet mode allows the processor to
request a number of words with one set of status.  In packet mode,
one, two or four 32-bit words from consecutive memory locations are
requested.  The processor will start a packet access by placing the
address of the packet and the packet size on the local bus.  The
packet addresses wrap around blocks which are packet size aligned.
If the starting address of a four-word packet is '0004'x then the
remaining addresses are '0008'x, 000C'x, and '0000'x.

      Burst mode is the Intel 80486 version of packet mode. In burst
mode, the processor can request two, three, or four double words (32
bits) from consecutive memory locations. The burst mode interface is
slightly different than the packet mode interface in that burst
addresses wrap around two-word blocks.  If the starting address of a
burst of four words is '0004'x, then the remaining addresses are
'0000'x, '000C'x, and '0008'x.  Page mode is an operational mode of
the memory where accesses are made using different column addresses
but the same row address.  Page mode generally provides a performance
enhancement over the normal operation.

      Typically, memory requests from the system processor are
handled as single word transfers, with a word being 8 bits, 16 bits,
or 32 bits, depending on the width of the processor's data bus.  The
system's memory controller must decode a set of status for each
transfer.  During the time the memory controller is decoding the
status, the bus is busy but is not being used for data transfer
operations.  If multiple memory transfers could be decoded from one
set of status, then the overhead on the bus could be reduced and the
bus bandwidth could be more efficiently utilized and could provide a
means of handling 64-bit words.  The concept described herein
utilizes this approach by providing a means of increasing the
efficiency of the bandwidth by utilizing two-way interleaving with a
page mode for packet mode accesses.

      In packet mode operations, the controller decodes one set of
status for the entire packet.  Using the starting address of the
packet and the packet size information, the controller can determine
the addresses of the remaining transfers without waiting on the pro
cessor to provide such information.  In packet mode, the memory
controller starts a cycle to one bank of memory, and before the cycle
is completed, the memory controller starts a cycle to another bank of
memory.  Interleaving on the low-order address bit allows the memory
controller to alternate between two banks of memory.  Since the
packet addresses wrapped around the packet remain in...