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Self Aligned Buried Emitter Schottky Collector Transistor

IP.com Disclosure Number: IPCOM000122449D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Hsieh, CM: AUTHOR [+4]

Abstract

A method is given for fabricating a self-aligned Schottky collector transistor with a buried emitter layer. This design is a good candidate for cost performance circuit application.

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Self Aligned Buried Emitter Schottky Collector Transistor

      A method is given for fabricating a self-aligned Schottky
collector transistor with a buried emitter layer.  This design is a
good candidate for cost performance circuit application.

      The process steps are as follows for the base of an NPN
transistor:
      (1)  An N+ layer 10 is formed on a P- substrate 11 by arsenic
ion implantation.
      (2)  Grow a thin epitaxial layer 12 of 3,500 o and form trench
isolation 14.
      (3)  Deposit a layer of undoped polysilicon 16 of about 3,500 o
and grow a thermal oxide 18 of about 800 o, as shown in Fig.  1.
      (4)  With a photoresist mask, phosphorus ions are implanted
into the polysilicon to form N+ reach-through 20.
      (5)  Similarly, with a photoresist mask, boron ions are
implanted ion to polysilicon layer to form P+ extrinsic base 22.
      (6)  Define polysilicon layer by RIE and cover CVD nitride 24
over it.
      (7)  RIE open SBD collector window and drive in both N+ and
Pfrom polysilicon into monocrystalline silicon, as shown in Fig. 2.
      (8)  Implant boron ions into this collector window to form
intrinsic base 26.
      (9)  Sidewall formation 28 and SBD metallization 30 (Hf or Y).
      (10) Contact hole opening and stud formation 32, as shown in
Fig.  3.