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Schottky Collector Transistor with Reduced Parasitics

IP.com Disclosure Number: IPCOM000122452D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Hsieh, CM: AUTHOR [+4]

Abstract

For a conventional Schottky collector transistor with a collector-up version, the emitter area is much larger than the collector area and the parasitic portion increases a lot in B/E diffusion capacitance. This results in lower current gain and cut-off frequency.

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Schottky Collector Transistor with Reduced Parasitics

      For a conventional Schottky collector transistor with a
collector-up version, the emitter area is much larger than the
collector area and the parasitic portion increases a lot in B/E
diffusion capacitance.  This results in lower current gain and
cut-off frequency.

      Here, we propose a method of fabricating a better performance
device with most of the parasitic area of the extrinsic base-to-
emitter junction eliminated.  In addition, the current gain will be
enhanced by doping Ge in the base layer by using the low temperature
epitaxy technique.  The process steps are listed as follows for the
case of a p-type base:
      (1)  An N+ layer 10 is formed on a P- substrate by a
conventional epitaxial growth.  If the circuit application is limited
to a direct-coupled emitter-grounded NOR circuit only, then we can
use an N+ substrate without an epi layer as our emitter.
      (2)  Grow a thermal oxide 12 and CVD a nitride layer 14 and
then pattern etch the active device area.
      (3)  LTE growth of extrinsic base 16 and intrinsic base 18
layers, and CVD oxide 20 and nitride 22 layer, as shown in Fig.  1.
      (4)  Define the LTE base layer outside the device area by RIE.
      (5)  Open the collector window by RIE etching the nitride and
oxide layers.
      (6)  RIE etching half-way into the extrinsic base of P++ layer,
then oxidize the remaining P++ layer by using t...