Browse Prior Art Database

Emitter Region Without Silicon Surface Damage

IP.com Disclosure Number: IPCOM000122456D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Beyer, KD: AUTHOR [+3]

Abstract

In the presence of double polysilicon self-aligned high performance bipolar structure, RIE etching of the polysilicon layer has to be applied in order to form the intrinsic base and the emitter region. During this RIE etching step, the silicon surface can be damaged in the emitter region.

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Emitter Region Without Silicon Surface Damage

      In the presence of double polysilicon self-aligned high
performance bipolar structure, RIE etching of the polysilicon layer
has to be applied in order to form the intrinsic base and the emitter
region.  During this RIE etching step, the silicon surface can be
damaged in the emitter region.

      A semiconductor process is described which does not induce
silicon surface damage in the emitter region for a bipolar device
with an extrinsic polysilicon base.  As shown in Fig. 1, an intrinsic
polysilicon layer 4 with a thickness of about 200 nm is deposited on
a device subcollector isolated by trenches with an oxide sidewall 1,
a polysilicon or glass fill 2 and a CVD cap 3.  On top of polysilicon
4, a CVD SiO2 island 5 about 200 nm thick is formed.  This oxide
island is covered by a thin polysilicon layer 6 having a thickness of
about 50 nm and acting as a RIE stop layer and a 100 nm CVD
Si3N4 layer 7 acting as a polishing stop layer. In addition, a CVD
TEOS sidewall spacer 8 is formed around the CVD SiO2 island 5 to
prevent boron doping near the emitter region during the boron
implantation to form extrinsic base.

      In the next step, as shown in Fig. 2, a sequence of CVD layers
is deposited consisting of a 50 nm thick oxide mask layer 9, BSG
(borosilicate) layer 10 of a thickness matching the height of layer
5, a 50 nm Si3N4 RIE stop layer 11 and a 100 nm Si3N4 polishing
stop layer 12.

      As shown i...