Browse Prior Art Database

Level Sensitive Scan Design Latch Trigger Implementation of Microprocessor Architecture

IP.com Disclosure Number: IPCOM000122459D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 109K

Publishing Venue

IBM

Related People

Carey, M: AUTHOR

Abstract

This article documents a CMOS implementation of a microprocessor architecture currently implemented in a bipolar technology. This new design has a significantly different data flow and simplified, more straightforward interface than its predecessor. In addition, it is a pure latch/trigger Level Sensitive Scan Design (LSSD).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Level Sensitive Scan Design Latch Trigger Implementation of Microprocessor
Architecture

      This article documents a CMOS implementation of a
microprocessor architecture currently implemented in a bipolar
technology.  This new design has a significantly different data flow
and simplified, more straightforward interface than its predecessor.
In addition, it is a pure latch/trigger Level Sensitive Scan Design
(LSSD).
BASIC FEATURES
-    Dynamic (per instruction basis) PROM/ROS Next Instruction Select
-    Non-Pipelined Design
-    Separate Instruction and Data Address Spaces
-    Separate Buses for Data Input/Instruction Input/Data Output
-    64K Instruction Address Space Internal
-    160-Byte Data Address Space Mapped as Follows:
      -    128-Bytes of LSRs (Local Storage Registers/indirectly
addressed by instructions)
      -    32 Bytes of XRs (External Registers/explicitly addressed
by instructions)
-    3-Bit Condition Code Register (updated at end of all Data
Manipulation Instructions (except Copy)
      -    CC(0) = CARRY
      -    CC(1) = EQUAL/ALL
      -    CC(2) = ZERO/NONE
-    Twelve Instruction Types
      -    Unconditional Branches (3)
                Branch, Branch and Link, Branch and Link Return
      -    Conditional Branches (3)
           -    Branch on Bit XR, Branch on Bit LSR, Branch on
Condition
      -    Data Manipulation Instructions (4)
           -    LSR to LSR, LSR Immed., XR Immed., Copy
      -    Control Store Read Ops (2)
           -    Read CS Format 0, Read CS Format 1
-    A sophisticated MP clock Start/Stop/Step Mechanism.
NOTES
1)   CS   = Control Store
      ROS  = On-chip Read-Only Memory
      PROM = Off-chip Programmable Read-Only Memory
      NSI  = Next Sequential Instruction
      BRI  = Branch Target Instruction
2)   A $ after a name denotes an I/O
DATA FLOW

      The following discussion refers to the figure.
Major functional blocks in the data flow are as follows:
-    ROSDATA REG - holds the output of on-chip ROS
-    PROMDATA REG - holds the output of off-chip PROMs
-    PROMSEL REG - holds the values of the +...