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Multi-address Control Logic for S/370 Channel Interface

IP.com Disclosure Number: IPCOM000122472D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 113K

Publishing Venue

IBM

Related People

Mizukoshi, Y: AUTHOR

Abstract

Disclosed is a multiple address control logic for S/370 channel interface. The control unit checks the selection address from the channel, and decides whether it should propagate the selection or respond to the selection. In case the selection address is for itself, the control unit's operation proceeds to command recognition and status response. The described logic can control the multiple subchannel address interface with no restriction. This capability can be applied to the transparent channel extend mechanism.

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This is the abbreviated version, containing approximately 52% of the total text.

Multi-address Control Logic for S/370 Channel Interface

      Disclosed is a multiple address control logic for S/370
channel interface. The control unit checks the selection address from
the channel, and decides whether it should propagate the selection or
respond to the selection. In case the selection address is for
itself, the control unit's operation proceeds to command recognition
and status response. The described logic can control the multiple
subchannel address interface with no restriction. This capability can
be applied to the transparent channel extend mechanism.

      Control units that have a multiple subchannel address are
usually defined in a small continuous address range of the host
processor, because one control unit does not control a lot of I/O
devices and the limited number of addresses helps make for easier
implementation of the address compare logic. However, for the channel
extend mechanism, it is important to control the multiple subchannel
address individually with no restriction. And for performance
improvement, the hardware should handle the Initial Selection
Sequence by itself (address compare, command receive and status
response).

      The described control logic contains the following tables to
handle the multiple subchannel address and to respond with the
initial status. All tables have 256 entries that relate to the
maximum subchannel address.
      Address Enable Table
      -Each entry contains 1 bit of information that indicates that
the selected address is either enable (proceeds with selection
sequence) or disable (propagates selection).
      -Microcode maintains this table, and hardware only refers to
this table.
      Device Status Table
      -Each entry contains 8-bit device status and 1 bit information
that indicates whether the Initial Status Table is used or not.
      -When the Initial Status Table is disabled, the 8-bit device
status is always returned to initial selection for all the received
commands. This method is effective for stacked status or busy
conditions.
      -Microcode maintains this table, and hardware only refers to
this table.
      Initial Status Table
      -Each entry contains 256 of 8-bit initial status, each initial
status is provided for the host processor's command accordingly, and
the initial status is returned when this table is not disabled by the
Device Status Table.
      -Microcode maintains this table, and hardware only ref...