Browse Prior Art Database

Data Count Control Logic for S/370 Channel Data Streaming Mode

IP.com Disclosure Number: IPCOM000122484D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 139K

Publishing Venue

IBM

Related People

Mizukoshi, Y: AUTHOR

Abstract

Disclosed is a data count control logic for S/370 channel data streaming mode. Data streaming mode can perform the high speed data transfer since there is no signal handshake between the channel and the control unit; however, the control unit should check the requested tag count (SVCIN, DATIN), received tag count (SVCOUT, DATOUT) or stop indication (CMDOUT). The described logic can control the data transfer request, stop detection and error detection immediately, and is implemented with a small amount of circuitry.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Data Count Control Logic for S/370 Channel Data Streaming Mode

      Disclosed is a data count control logic for S/370 channel
data streaming mode. Data streaming mode can perform the high speed
data transfer since there is no signal handshake between the channel
and the control unit; however, the control unit should check the
requested tag count (SVCIN, DATIN), received tag count (SVCOUT,
DATOUT) or stop indication (CMDOUT). The described logic can control
the data transfer request, stop detection and error detection
immediately, and is implemented with a small amount of circuitry.

      At the data streaming mode, the data transfer request from the
control unit and the response from the channel are independent, and
the request tag count precedes the response tag count due to the
channel response delay and cabling signal delay. A conventional
control method uses two independent data counters, one for counting
the request tag from the control unit itself and the other for
counting the receive response tag from the channel, and, in addition,
it uses the comparator of these counters for validity checking. This
method needs a large amount of circuitry for a large-size data
transfer capability (e.g., 64 KBytes).

      The disclosed control logic reduces both circuit volume and
system loss time of error recovery. Figure 1 shows the block diagram.
This method uses one full-size counter for actual transferred data
count, one small-size counter for the difference between request
count and response count, and a partial comparator.

      COUNTER-A in Figure 1 is a 16-bit synchronous down counter for
indicating actual transferred data count. Counter size matches with
data transfer size.
      -Microcode sets the counter contents, maximum receivable data
count at host write operation, transfer ready data count at host read
operation, prior to the data transfer (controlled by COUNT_LOAD_EN
signal).
      -During a data transfer sequence, decrementing is by SVCOUT or
DATOUT until CMDOUT is received (controlled by COUNT_DOWN_EN_1
signal).
      -Counter contents show the residual data count.

      COUNTER-B in Figure 1 is a 4-bit synchronous up-down counter
for checking the channel tag response validity. Counter size is
determined from the cable length and transfer rate.
      -Counter contents are reset to zero prior to the data transfer
(controlled by COUNT_RESET signal).
      -Duri...