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Bit Manipulation Facility for a Parallel Architecture

IP.com Disclosure Number: IPCOM000122492D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 118K

Publishing Venue

IBM

Related People

Larsen, LD: AUTHOR

Abstract

This article describes a facility for allowing individual bits to be moved and otherwise manipulated in a microprocessor that is intended primarily to perform parallel arithmetic operations. Two classes of manipulation are provided. 1. A general bit move function allows an individual bit to be selected from a source register and shifted into the high-order bit position of a destination register. The remaining destination register bits are moved one bit position right to accommodate the selected bit, and the low-order bit is discarded. 2. Simple logic functions can be performed involving pairs of bits taken from different source registers. Operations of this type take the form: Bit from Reg A * Bit from Reg B -> High-order bit of Reg A

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This is the abbreviated version, containing approximately 52% of the total text.

Bit Manipulation Facility for a Parallel Architecture

      This article describes a facility for allowing individual
bits to be moved and otherwise manipulated in a microprocessor that
is intended primarily to perform parallel arithmetic operations.  Two
classes of manipulation are provided.
1.   A general bit move function allows an individual bit to be
selected from a source register and shifted into the high-order bit
position of a destination register.  The remaining destination
register bits are moved one bit position right to accommodate the
selected bit, and the low-order bit is discarded.
2.   Simple logic functions can be performed involving pairs of bits
taken from different source registers. Operations of this type take
the form:
           Bit from Reg A * Bit from Reg B -> High-order bit of Reg A

      A variation is provided whereby both forms of manipulation can
be used in conjunction with moving bits to and from external logic.

      The specific mechanism proposed for accomplishing bit
manipulation consists of two elements:
1.   Bit manipulation logic is added to the conventional (parallel)
ALU to enable it to select one or two individual bits from a source
register or registers. The bit or bits selected are operated on by
additional new logic (the Bit Logic Unit or (BLU) and the resulting
bit is directed to the high-order bit position of a destination
register.  The BLU also causes the remaining destination register
bits to shift one place to the right to accommodate the result.  The
BLU is capable of performing AND, OR, and XOR functions on two bits,
and bit inversion on a selected single bit (or the result of a
logical operation).
2.   A special-purpose Manipulate instruction is provided which has
fields to specify individual source bits within specific registers,
the destination register address, and the nature of the operation to
be performed by the BLU.

      A variation of the operating modes just described is made
possible by breaking the path from the BLU output to the destination.
Then, the BLU output is sent to an external destination and a bit
from an external source is directed to the internal destination
register.  The option to select an external path will be controlled
by a bit in the Manipulate instruction.  This may be (for example) an
External Path Select (ES) bit that will, when on, activate the
external serial path instead of the internal one.  In all other
r...