Browse Prior Art Database

Interconnection for Testing Chips/Wafers

IP.com Disclosure Number: IPCOM000122499D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Related People

Ingraham, AP: AUTHOR [+3]

Abstract

A technique is described to test chips and wafers with a temporary interconnection to a test fixture. The interconnection, an anisotropic conducting sheet that conducts electricity only in the Z direction, provides an interface connection that leaves the solder bumps (C4s) or wire bond pads intact and free of damage on the device being tested.

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Interconnection for Testing Chips/Wafers

      A technique is described to test chips and wafers with a
temporary interconnection to a test fixture.  The interconnection, an
anisotropic conducting sheet that conducts electricity only in the Z
direction, provides an interface connection that leaves the solder
bumps (C4s) or wire bond pads intact and free of damage on the device
being tested.

      The test assembly in the figure is constructed of chip/wafer
carrier 1 that contains all the required wiring from the I/O pads on
a device to an appropriate connector system to a tester 2.  An
anisotropic conductor polymer 3 containing gold, graphite, silver,
copper or other conductive particles is applied to the C4 pad areas
of the carrier.  A device 4 to be tested is placed on the conductive
polymer with the I/O pads aligned to the appropriate pads on the
carrier.  This device is held in place with a clamping tool 5 to
provide good intimate contact between the C4s and their corresponding
pads.