Browse Prior Art Database

DASD Data Protection During Write Fault Error Handling

IP.com Disclosure Number: IPCOM000122517D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Guttmann, JE: AUTHOR [+2]

Abstract

Described is a method of protecting stored data within a Direct Access Storage Device (DASD), from further destruction during error recovery procedures, when determining the source of write fault errors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

DASD Data Protection During Write Fault Error Handling

      Described is a method of protecting stored data within a
Direct Access Storage Device (DASD), from further destruction during
error recovery procedures, when determining the source of write fault
errors.

      This invention allows hardware safety circuits to be disengaged
while preventing any further destruction of DASD data as the nature
of the write fault is determined.  The invention involves the support
of both hardware and software.

      The hardware provides a write circuit deselection mechanism
which is controlled by the software.  This is done by supplying a
register bit in the DASD hardware logic which, when set to the
appropriate value by the software, overrides the normal operation of
the write circuit and forces the circuit into a non-writable state.
The software can now utilize this hardware feature when write fault
error recovery procedures are invoked.

      The figure shows the actual usage of the invention.  As seen in
the diagram, point A is when the error is detected, which causes the
safety protection of the hardware to prevent any further writes
(Safety Wrt Prevent).  The software write fault error recovery
procedure is then invoked.  Before the software attempts to determine
the nature of the error, the new write circuit override register bit
(Invention Wrt Prevent) is set to the appropriate level to force the
write circuits to an inactive state.  Point B is the tim...