Browse Prior Art Database

Bus Monitor Using DRAM Interface for a Harvard Style Computer Architecture

IP.com Disclosure Number: IPCOM000122527D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Related People

Carnevale, MJ: AUTHOR [+4]

Abstract

A method for monitoring the activity of a Harvard-style architecture processor is disclosed. A debug module reconstructs the cycle address from the processor memory lines, the data from the data lines and processor-supplied byte enables and determines the cycle type from processor-supplied cycle activity outputs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Bus Monitor Using DRAM Interface for a Harvard Style Computer Architecture

      A method for monitoring the activity of a Harvard-style
architecture processor is disclosed.  A debug module reconstructs the
cycle address from the processor memory lines, the data from the data
lines and processor-supplied byte enables and determines the cycle
type from processor-supplied cycle activity outputs.

      The figure depicts the signal interface between a Harvard-style
architecture processor (one with an instruction and data store) and a
debug module designed to monitor its activity.  The control store has
10 address lines, and the data store, which is split into a high and
low bank, has 10 address lines for each of the 2 banks. When the CS
CAS signal is valid, the 10 address lines for the control store
indicate the DRAM's column address corresponding to the memory
reference.  When a CS RAS signal is valid, the CS ADDR lines
represent the DRAM's row address corresponding to the memory
reference.  The data store signals work much the same way.  The
generation of the memory control signals is controlled by registers
which are used to determine if a processor address is in memory, and,
if so, which bank of memory.

      The processor informs the debug module of its current activity
via the 4 Processor Activity lines.  They are encoded as follows:
      -  B'0000' No activity
      -  B'0001' Instruction Fetch from Input/Ouput Adapter (IOA) bus
      -  B'0010' Data Read from IOA bus
      -  B'0011' Data Write to IOA bus
      -  B'0100' Data Read from Control Store
      -  B'0101' Data Read from Data Store
      -  B'0110' Data Write to Control Store
      -  B'0111' Data Write to Data Store
      -  B'1000' Instruction Fetch from Control Store
      -  B'1001' Instruction Fetch from Data Store
      -  B'1010' DMA Read from Control Store
      -  B'1011' DMA Read from Data Store
      -  B'1100' DMA Write to Control Store
      -  B'1101' DMA Write to Data Store
      -  B'1110' Debug Module Register Read
      -  B'1111' Debug Module Register Write

      This information is vital in rebuilding the original process...