Browse Prior Art Database

Data Processing System

IP.com Disclosure Number: IPCOM000122529D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 9 page(s) / 299K

Publishing Venue

IBM

Related People

Carnevale, MJ: AUTHOR [+4]

Abstract

I/O Processor (IOP) design is usually driven by ever increasing requirements for more performance. This article describes a high performance, 32-bit pipelined IOP implementing Harvard computer architecture. The IOP has integrated bus and DRAM controllers all on a single chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 32% of the total text.

Data Processing System

      I/O Processor (IOP) design is usually driven by ever
increasing requirements for more performance.  This article describes
a high performance, 32-bit pipelined IOP implementing Harvard
computer architecture.  The IOP has integrated bus and DRAM
controllers all on a single chip.

      Fig. 1 is a high level data flow diagram of a unique pipelined
processor.  All data buses are shown as a single line with an arrow
indicating the direction of the data flow.  The single lines can
represent data flows ranging from 2 bytes to 72 bytes.

      The memory controller (interface) generates two distinct memory
address buses for the purpose of dividing the memory into two
sections; one section is where instructions should reside (control
store), and the other section is where data should reside (data
store).  When memory is configured and controlled like that described
(two separate address buses), processing performance is gained
because instruction prefetching and data storing/writing to memory
generally do not interfere with each other. Configuration registers
allow dynamic alteration of where control store ends and where data
store starts.
INSTRUCTION PREFETCHING

      The I Counter (Fig. 1) provides a 32-bit address to the Memory
Interface for the purpose of prefetching instructions when the
processor is executing sequential code.  In sequential mode, the I
counter is updated by the Instruction Assembly Buffer (IAB) which has
a 16-byte prefetch buffer. Instructions from the Memory Interface,
fetched from the storage address provided by the I Counter, enter the
IAB and are directed toward the proper bytes contained in the
prefetch buffer.  Four bytes are always fetched.  In non-sequential
mode (instructions that alter the program counter) the IAB works
essentially the same, but the I Counter first must be loaded with
data either from memory or the output of the Effective Address Adder
(EA Adder).  After the I Counter has been loaded, the machine returns
to sequential mode and operates as described above.  As instructions
enter the IAB, the OP code is examined to determine the instruction
length.  If a complete instruction is contained in the prefetch
buffers, the I Counter is incremented by the instruction length and
the instruction is passed to the Decode block in Fig. 1.
MICRO-INSTRUCTION FORMAT

      The Decode block (Fig. 1) receives aligned instructions from
the IAB (anywhere from 2 to 10 bytes) and generates
micro-instructions that are a fixed 158 bits in length (Fig. 2).  The
fields contained in the micro-instruction will now be described.  The
A, O, X, S, and C fields shown in Fig. 2 are all one-bit fields
and are used by the instruction pipeline hardware to sequence the
micro-instructions through the pipeline.  The importance of these
fields will be evident later.  Fig. 3 shows the bit definitions of
the A UNIT field of the micro-instruction.  Referring to Fig. 1, the
Mux3,...