Browse Prior Art Database

Pseudo Cache Based Architecture

IP.com Disclosure Number: IPCOM000122530D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 5 page(s) / 212K

Publishing Venue

IBM

Related People

Pescatore, JC: AUTHOR [+2]

Abstract

This article describes the architecture for a processor system with a high speed buffer which provides the following function: . Eliminates the performance degradation due to a directory access and compare in the Classical Cache. . Eliminates the performance degradation due to line transfers as a result of cache misses. . Decreases the number of bytes transferred during a line transfer that occurs as a result of a cache parity error. . Provides a very high hit to miss ratio for instruction- intensive processors. . Reduces the complexity of the system design compared to the Classical Cache. . Detects and handles errors during a storage operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

Pseudo Cache Based Architecture

      This article describes the architecture for a processor
system with a high speed buffer which provides the following
function:
       .   Eliminates the performance degradation due to a directory
access and compare in the Classical Cache.
       .   Eliminates the performance degradation due to line
transfers as a result of cache misses.
       .   Decreases the number of bytes transferred during a line
transfer that occurs as a result of a cache parity error.
       .   Provides a very high hit to miss ratio for instruction-
intensive processors.
       .   Reduces the complexity of the system design compared to
the Classical Cache.
       .   Detects and handles errors during a storage operation.

      The high level diagram of the pseudo-cache-based architecture
is shown in Fig. 1.  The architecture employs the following key
elements:
      .    Main Storage (1)
      .    Storage Control (2)
      .    Direct Memory Access Adapters (3)
      .    Input-Output Devices (4)
      .    Pseudo-Cache (5)
      .    Central Control Unit (6)

      Main Storage (1) is composed of up to 16 Megabytes of dynamic
random-access memory (DRAM) organized as a 40-bit-wide word which
contains 32 data bits and 8 check bits.  The 8 check bits are used
for double-bit error detection and single-bit error correction (ECC).
The Main Storage is shared by Direct Memory Access Adapters (3),
Input- Output Devices (4) which operate through the Central Control
Unit (6).  The Storage Control (2) arbitrates and provides access to
the storage users.

      The Pseudo-Cache (5) is composed of fast static random-access
memory (SRAM) which is mapped into the first 1 megabyte of address
space.  The first 1 megabyte of Main Storage (1) is used as backing
storage for the Pseudo-Cache (5).  When a storage user performs a
read operation to any address within the first 1 megabyte of storage,
the data is read from the fast static random-access memory of the
Pseudo- Cache.  A parity check is performed on the data which is read
from the Pseudo-Cache.  If the parity check does not indicate an
error, the operation proceeds.  If the parity check indicates an
error, then the Storage Control (2) transfers four bytes of data from
the Main Storage (1) to the corresponding location in the
Pseudo-Cache (5). If the parity error was caused by a soft failure in
the static RAM, the transfer of data from the Main Storage to the
Pseudo-Cache will correct the error.  The read cycle is then rerun,
and the corrected data is read from the Pseudo-Cache.  If the parity
error was caused by a hard failure in the static RAM, the transfer of
data from Main Storage to the Pseudo-Cache will not correct the
error. When the read cycle is rerun, another parity error will be
detected and hard error indication will be sent to the storage user.

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