Browse Prior Art Database

Interleave Model

IP.com Disclosure Number: IPCOM000122531D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Bean, BM: AUTHOR [+4]

Abstract

Disclosed is a hardware mechanism for modeling the activity of one resource in a system containing multiple requestors. Several of the requestors may have operations in progress simultaneously which use the resource. The mechanism disclosed here is used to predict whether a resource will be available in future cycles. This availability information is one of the criteria used to determine whether or not a requestor will be granted priority in the current Cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Interleave Model

      Disclosed is a hardware mechanism for modeling the
activity of one resource in a system containing multiple requestors.
Several of the requestors may have operations in progress
simultaneously which use the resource. The mechanism disclosed here
is used to predict whether a resource will be available in future
cycles. This availability information is one of the criteria used to
determine whether or not a requestor will be granted priority in the
current Cycle.

      This hardware implementation models the activity of the memory
partitions, referred to as interleaves, which make up a second-level
(L2) cache.  The interleave model is used in determining priority for
requestors which need to read or write the L2 cache and therefore
will be busying the memory interleaves.  It allows requestors to be
granted priority as efficiently as possible, while guaranteeing that
no two operations will attempt to access the same interleave in the
same cycle, which is an error condition (called an "interleave
conflict").

      Each interleave is modeled by one shift register. Successive
bits of a register represent successive future cycles of activity for
that interleave.  All of the information needed to know a requestor's
future pattern of interleave usage - operation type (fetch, store,
etc.), starting interleave, and operation length (number of cycles to
read or write) - are known at the time the request is granted
priority.  This information is used to load 1's into the shift
registers making up the interleave model in such a way as to show all
future cycles where the interleaves will be busied as a result of
executing this specific request (as shown in Fig. 1).  Once a pattern
of fut...