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Enhanced Addressing Error Detection System

IP.com Disclosure Number: IPCOM000122546D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 7 page(s) / 223K

Publishing Venue

IBM

Related People

Karp, JM: AUTHOR [+2]

Abstract

This article describes a technique to implement address error checking as part of a memory error correction design, without requiring additional memory storage and without impairing the data correction capability of the base code. The technique was tailored to a memory system design utilizing a 4-bit-wide memory chip to provide superior error detection capability at reduced costs as compared to existing techniques.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Enhanced Addressing Error Detection System

      This article describes a technique to implement address
error checking as part of a memory error correction design, without
requiring additional memory storage and without impairing the data
correction capability of the base code. The technique was tailored to
a memory system design utilizing a 4-bit-wide memory chip to provide
superior error detection capability at reduced costs as compared to
existing techniques.

      Memory systems that are constructed with 4-bit memory chips and
4-bit driver modules are susceptible to multiple bit errors with a
single "chip" kill or module failure. Such memory systems are most
effectively protected from these module or chip failures by error
correction methods that are also based upon 4-bit symbols.
Additionally, it is most common to use single error correction,
double error detection (SEC-DED) codes in such memory systems. Such
codes correct and/or detect errors only in the data bits and the
error correction parity bits that are retrieved from the memory unit.

      On occasion the address bits are in error (they are modified by
the transport circuits/buses external to the memory chips or are
modified internally by the memory chip address circuits).  Such
errors will go undetected by the common error correction codes and
methods discussed above. This invention teaches an enhanced SEC-DED
error correction code methodology and implementation that provides
the ability to detect 93.75% of these type of addressing errors. This
detection feature is accomplished without impairment to the SEC-DED
properties of the base data error correction code and without
requiring additional memory storage.

      The base ECC is a 16-ary (7,4) SEC-DED code.  We add one
additional 4-bit symbol producing a new 16-ary (8,5) SEC-DED code
with addressing error detection capability. This added 4-bit symbol
is precomputed as a function of the address value that will be
associated with the storage to memory of the resultant codeword.  The
encoder/decoder block diagram for this enhanced error correction
system is shown in Figure 1.

      This added 4-bit symbol is the parity symbol from the 16-ary
distance 2 (6,5) error detection code.  This code processes the 20
address bits as 5 4-bit symbols, producing a single 4-bit parity
symbol.  This single 4-bit parity symbol is determined according to
the rules given in Figure 2.

      This single 4-bit parity symbol (the address key bits) is
combined with the 4 data symbols and encoded (in the PARITY BIT
GENERATOR) to produce the 3 SEC-DED parity symbols.  The encoding
equations are given in Figure 3.  The 4 data symbols and the 3 parity
symbols (28 total bits) are stored in memory.

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