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Main Address Transition Detection Circuit With Reduced Output Pulse Width

IP.com Disclosure Number: IPCOM000122556D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Girard, P: AUTHOR

Abstract

Disclosed is an improvement of conventional Main Address Transition Detection (ATD) circuits that are placed in asynchronous Static Random Access Memories (SRAMs) to generate an on-chip clock pulse each time one address or more varies. In the proposed circuit the first edge of the output pulse is used to cut off the current in the incoming branches and speed up the reset of the circuit whereas in a conventional circuit the output pulse is determined by the input pulse width.

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Main Address Transition Detection Circuit With Reduced Output Pulse
Width

      Disclosed is an improvement of conventional Main Address
Transition Detection (ATD) circuits that are placed in asynchronous
Static Random Access Memories (SRAMs) to generate an on-chip clock
pulse each time one address or more varies.  In the proposed circuit
the first edge of the output pulse is used to cut off the current in
the incoming branches and speed up the reset of the circuit whereas
in a conventional circuit the output pulse is determined by the input
pulse width.

      A schematic diagram of the new circuit is shown in Figure 1.
Compared to conventional circuits, one NFET device (N1A, N2A.... NXA)
has been added in each of the input branches. The gate of this device
is driven by a NAND gate fed by the input signal of this branch and
a global feedback signal RX similar to the output signal of the main
ATD. The NAND realizes a local feedback loop because it cuts off only
the active branches. If no signal is present on the input line, the
additional FET stays on. A main feedback loop is made of a delay
chain and two wide PFETs that reset signal on node R1. A small FET
device P1 insures the DC high voltage on node R1 in the quiescent
state.

      The behavior of the circuit will be explained from the
waveforms of Figure 2 where the response of the circuit to an input
pulse is shown. The rising edge of the input pulse (assuming I1)
triggered the falling edge of R1 and, thu...