Browse Prior Art Database

Fast Access of Data on Unaligned Address Boundaries

IP.com Disclosure Number: IPCOM000122560D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Carnevale, MJ: AUTHOR [+4]

Abstract

A method to increase performance of mutiple-byte data buses when it is required to access data words across address boundaries is disclosed. It is best suited, but not limited, to multiple banks of random access memory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fast Access of Data on Unaligned Address Boundaries

      A method to increase performance of mutiple-byte data
buses when it is required to access data words across address
boundaries is disclosed.  It is best suited, but not limited, to
multiple banks of random access memory.

      A way to speed up accesses which cross a physical address
boundary is to split the bus into smaller-width sub-words and provide
different address signals to the memory modules which form these
smaller sub-words.  An example would be to split a 32-bit word into
two 16- bit-wide sub-words or four 8-bit-wide sub-words.  The address
given to the memory modules which form each sub-word will be either
the original address, or the original address + 1.  The data
sub-words that come off the bus must then be swapped such that the
significant sub-words are ordered correctly.  Fig. 1 shows the
logical circuit connections, for example, where a bus is being
divided into two parts.

      As an example of the function which must be performed by the
memory controller, assume the processor data bus is 32 bits wide, and
the memory is broken into two 16-bit sub-words.  Further, assume
addressing is done on an 8-bit basis so that the first word of memory
is at address 0 and the second is at address 4, etc.  If the
processor requests a word at address 0, the memory controller simply
passes the same address to both banks of memory and returns the high
and low half of the data from the respective banks.  If...