Browse Prior Art Database

Multiple-JTAG Scan Path Interface Circuit for Board Level Test

IP.com Disclosure Number: IPCOM000122575D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 145K

Publishing Venue

IBM

Related People

Casparian, MA: AUTHOR

Abstract

The purpose of this article is to provide the circuit designer, who is not familiar with the in's and out's of JTAG testing, with a ready-to- implement Multiple-JTAG Scan Path Board Interface. It presents a solution to supporting multiple 1149.1 paths until such time the IEEE approves draft P1149.3. The circuit is also a solution to the designer wishing to implement non-JTAG scan functions along with a single or multiple 1149.1 JTAG path.

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This is the abbreviated version, containing approximately 52% of the total text.

Multiple-JTAG Scan Path Interface Circuit for Board Level Test

      The purpose of this article is to provide the circuit
designer, who is not familiar with the in's and out's of JTAG
testing, with a ready-to- implement Multiple-JTAG Scan Path Board
Interface.  It presents a solution to supporting multiple 1149.1
paths until such time the IEEE approves draft P1149.3.  The circuit
is also a solution to the designer wishing to implement non-JTAG scan
functions along with a single or multiple 1149.1 JTAG path.

      A "hand-me-down" IBM PC/XT*/AT* and off-the-shelf JTAG software
will get the hardware-oriented designer off and running with working
code within a week with very little capital expenditure.

      The interface circuit is based upon two chips, such as Logical
Solutions Technology Inc.'s (LSTI) 74TC32 Control IC and 74TV16
Visibility IC.  See Fig. 1.  The Control IC inputs test vectors
(JTAG's TDI) into the circuit board, as well, generates test clocks,
chip enables, reset, etc.  The Visibility IC samples data (JTAG's
TDO) at various nodes for eventual comparison to expected states back
at the test controller.  The circuit board could be partitioned into
multiple JTAG Scan paths, such as 1, 2 ... N paths.

      A cost effective controller can be constructed by mounting an
Alpine Image System's (AIS) proTEST-PC card/software in an IBM PC/XT/
AT (or compatible) to convert one's PC into a Circuit Board Tester.

      Fig. 2 shows a set-up of attaching the proTEST-PC to a Card
Cage's backplane (i.e., VME-bus, Futurebus+, Multibus, etc.).  An
interface card is necessary to take the two proTEST-PC outputs and
apply line drivers to the signals in order to be able to drive them
onto the Card Cage's backplane.

      All AIS signals are buffered as they enter/exit the
"card-under- test" to ensure that each buffered input is pulled to
Vcc through a 2.2K ohm resistor.  This will prevent these lines from
floating when the board is not connected to the AIS system.  Once
buffered, the AIS signals go directly to the interface circuit
located on the "card- under-test."

      The interface circuit is shown in Fig. 3.  When the circuit
board is in normal operational mode, one wants the JTAG Control lines
disabled from the circuitry.  When the board is selected to operate
in test mode, one wants the JTAG control lines enabled.  To
accommodate this, an on-board comparator compares the board's address
to that loaded in by the proTEST-PC.  When a match is found, the
comparator outputs a low-active signal which is then fed into many 2
input OR gates.  The OR gates enable/disable the JTAG Control
signals.  When th...