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Browse Prior Art Database

Check Bit Write Back with Driver Interlock

IP.com Disclosure Number: IPCOM000122579D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR

Abstract

By using differential cascode voltage switch gates (XORs), check bits are generated for a data word as required to conclude a write operation in error correction code (ECC) systems. Check bits and data bits are written back to a memory array by strobed write back drivers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 88% of the total text.

Check Bit Write Back with Driver Interlock

      By using differential cascode voltage switch gates
(XORs), check bits are generated for a data word as required to
conclude a write operation in error correction code (ECC) systems.
Check bits and data bits are written back to a memory array by
strobed write back drivers.

      Fig. 1 shows a system wherein check bits are generated by
feeding incoming data words 10 (both true and complement) to cascode
voltage switch gates, e.g., Exclusive ORs (XORs) G1, G2, and G3, and
thence to inverters I1 and I2 and out of check bit generator 12 to a
strobed write driver, e.g., C2.  Strobe phases PR and PN are
generated in check bit ready circuit 14 from inputs ST and SC from an
XOR gate, e.g., G3.  Phases PR and PN may be generated to fire very
soon after the check bits are generated by proper tap-off from the
series of XOR gates in the check bit generators.  Data bit write back
drivers D1 are triggered by phases PR and PN to write into memory
array.  Similarly, check bit drivers C1 ...Ck are triggered by phases
PR and PN to write the check bits into memory array 16.

      Fig. 2 is a schematic of check bit ready circuit 14 which uses
differential outputs of an XOR gate, e.g., ST and SC, to generate
strobe signals PR and PN.  When inputs IN1 and IN2 are high, node N1
falls to ground potential when T7 or T8 turn on.  Inverter chains T1
through T6 and T9 through T12 then generate strobe phases PR and PN.
The circuit is...