Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Buried Interconnects Using Enhanced Lateral Etching of Doped Si and CVD Metal

IP.com Disclosure Number: IPCOM000122580D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Colgan, EG: AUTHOR [+3]

Abstract

Integrated circuit speeds and densities are becoming limited by the interconnections [*]. Buried interconnects can potentially improve circuit speeds by providing an extra wiring level, resulting in shorter average wire length. In addition, buried interconnects can potentially increase circuit densities, by allowing more chips to be wired than is possible with conventional interconnects.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 85% of the total text.

Buried Interconnects Using Enhanced Lateral Etching of Doped Si and
CVD Metal

      Integrated circuit speeds and densities are becoming
limited by the interconnections [*].  Buried interconnects can
potentially improve circuit speeds by providing an extra wiring
level, resulting in shorter average wire length.  In addition, buried
interconnects can potentially increase circuit densities, by allowing
more chips to be wired than is possible with conventional
interconnects.

      We propose a new process for fabricating local interconnects.
Lateral vias are formed using enhanced etching of heavily doped
n-type Si (1x1020 cm-3 or greater) and are then filled with CVD
metal.  A possible process flow is as follows:  The regions where
vias are to be formed are defined using a resist mask and ion
implantation of As at the appropriate depth.  In a bipolar process,
this could be done during the subcollector implant.  The As is
activated either with a separate anneal or during subsequent device
processing (Fig. 1a). After the Si processing is complete, vertical
via holes are etched down to the heavily As-doped regions, using
lithography and RIE, then lateral via holes are etched in the heavily
As-doped regions using RIE (Fig. 1b).  Lateral holes a few microns in
length have been etched in 1x1021 cm-3 As-doped Si using Cl2 RIE.
Finally, the holes are filled with CVD metal such as W (Fig. 1c).
Continuity has been demonstrated for CVD W in 5 um long lateral vias.
Ideally...