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Fuseless Non-volatile Ferroelectric Redundant Word and Bit Decoder

IP.com Disclosure Number: IPCOM000122581D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 119K

Publishing Venue

IBM

Related People

Tomashot, SW: AUTHOR

Abstract

A dynamic random access memory (DRAM) redundant word and bit decoder operates with a ferroelectric latch instead of fuses. Thin film ferroelectric capacitors for the latch having material, e.g., lead zirconate titanate (PZT), as polarizable dielectric, may be incorporated into the same plane with a DRAM integrated circuit or as structure disposed above the standard DRAM circuit. The decoders may be programmed or reprogrammed at any time from wafer level test to system usage. Thus, a means is provided for permanent correction of DRAM faults created during wafer processing or after chip assembly into modules, cards, boards, or systems and after use in systems.

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Fuseless Non-volatile Ferroelectric Redundant Word and Bit Decoder

      A dynamic random access memory (DRAM) redundant word and
bit decoder operates with a ferroelectric latch instead of fuses.
Thin film ferroelectric capacitors for the latch having material,
e.g., lead zirconate titanate (PZT), as polarizable dielectric, may
be incorporated into the same plane with a DRAM integrated circuit or
as structure disposed above the standard DRAM circuit.  The decoders
may be programmed or reprogrammed at any time from wafer level test
to system usage.  Thus, a means is provided for permanent correction
of DRAM faults created during wafer processing or after chip assembly
into modules, cards, boards, or systems and after use in systems.

      A ferroelectric latch, such as one described in Electronics
Magazine, Feb. 1988, pp 91-95, retains the state of a standard
complementary metal oxide silicon (CMOS) latch by polarizing a pair
of ferroelectric capacitors during power down and resetting the latch
to its former state by reading the polarization state of the
capacitors during power up.  This latch circuit is used as a basic
element in a new DRAM redundant word decoder shown in Fig. 1.  A bit
decoder may be built to operate in a similar fashion and is therefore
not described.  The word decoder is comprised of five circuits:
precharge circuit 10, redundant wordline circuit 12, ferroelectric
master enable latch 14, ferroelectric address latch 16 for each row
address bit, and a read/ write control circuit 18 for programming the
decoder.

      Precharge circuit 10, comprised of two P-type transistors Tp,
inverter I and N-type transistor Tn, conditions internal nodes A, B,
and C of the decoder in preparation for a next memory access cycle.
During normal operation, precharge line PRE is brought low during a
restore portion of a previous cycle which conditions nodes A, B, and
C low.  When an active cycle begins, PRE returns high and Nodes A, B,
and C float.  As the active cycle proceeds, row address true (T) and
complement (C) information is driven onto an address bus 19 and into
the redundancy decoders.  If an address stored in a ferrolectric
address latch 16 (shown also in Fig. 2) matches the incoming T/C
address, pull down legs of the address latch (transistors T1A, T2A
and T3A, T4A in Fig. 2) remain off and do not contribute to discharge
of...