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CMOS Compatible Lateral NPN Transistor

IP.com Disclosure Number: IPCOM000122582D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Daly, AJ: AUTHOR [+4]

Abstract

Because of low power dissipation for CMOS and high-speed driving capability of bipolar device, the future of BiCMOS VLSIs is very promising. However, adding a vertical bipolar device into CMOS will complicate the processing step and may degrade the performance of CMOS device. Here we propose a CMOS compatible lateral bipolar transistor, its performance although is lower than the state-of-art vertical bipolar transistor but more comparable to that of the current CMOS device. We believe this type of BiCMOS VLSI is useful for the application of the cost performance product. FABRICATION PROCESS STEPS: 1. Form N+ buried layer and grow N-epi on p-substrate waver 2. Channel stop I/I and ROX isolation 3. Multi-energy step P-/P+ I/I to form LNPN base and P-well for NMOS device 4.

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CMOS Compatible Lateral NPN Transistor

      Because of low power dissipation for CMOS and high-speed
driving capability of bipolar device, the future of BiCMOS VLSIs is
very promising.  However, adding a vertical bipolar device into CMOS
will complicate the processing step and may degrade the performance
of CMOS device.  Here we propose a CMOS compatible lateral bipolar
transistor, its performance although is lower than the state-of-art
vertical bipolar transistor but more comparable to that of the
current CMOS device.  We believe this type of BiCMOS VLSI is useful
for the application of the cost performance product.
FABRICATION PROCESS STEPS:
1.   Form N+ buried layer and grow N-epi on p-substrate waver
2.   Channel stop I/I and ROX isolation
3.   Multi-energy step P-/P+ I/I to form LNPN base and P-well for
NMOS device
4.   P+ reach-thru I/I for LNPN base and p-well of NMOS
5.   Gate oxide growth
6.   Pattern gate oxide
7.   Deposit CVD poly layer with N type doping
8.   Deposit PECVD oxide/nitride
9.   RIE define emitter region
10.  First emitter sidewall formation
11.  RIE define NMOS gate
12.  N- LDD for NMOS and collector extension I/I for LNPN
13.  Second sidewall for bipolar Tx, and first sidewall for FET
14.  I/I N+ collector, N+ source/drain and anneal
15.  Silicide formation
16.  Dielectric, contact opening and metalization

      By using the above process steps, we form an enclosed LNPN
transistor which is compatible to most...