Browse Prior Art Database

Interlocked Circuit Position Indicator

IP.com Disclosure Number: IPCOM000122584D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR

Abstract

A differential output position indicator is interlocked to its single- ended syndrome outputs for high-speed operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 84% of the total text.

Interlocked Circuit Position Indicator

      A differential output position indicator is interlocked
to its single- ended syndrome outputs for high-speed operation.

      Referring to Fig. 1, signals are generated on syndrome bus
lines S1T, S1C through SnT, SnC by differential cascode voltage
switch (DCVS) logic gates contained within syndrome generator 2.
Signals are generated by Exclusive ORs (XORs) 4, 6, and 8, then
buffered through pairs of inverters 10 and 12 to go out on lines S1T
and S1C of the syndrome bus.  A signal SY is a flag signal from
generator 14 sent to position indicators along the syndrome bus timed
by a pair of true and complement outputs SC and ST from XOR 8 (or
XOR6) on lines 16 and 18.  SY then closely follows signals on
syndrome bus lines S1T and S1C.

      One interlocked position decoder is shown in Fig. 1 having
decode devices T1, T2, T3, and T4 connected to the syndrome bus.
After syndrome lines become valid, node N2 falls or remains high and
node N1 either remains high or falls when signal SY enables a clocked
inverter comprised of transistors T13, T14, and T15.  Signals ERRT
and ERRC are generated by transistors T5 and T7, and T6 and T8,
respectively.  Devices T9 and T12 provide leakage protection by means
of a soft latch action.  Devices T10, T11, T17, and T16 perform
restore and circuit enable functions via input P.

      Fig. 2 is detail of SY generator 14 of Fig. 1.  Phase SRVD
enables the circuit by turning on n-ty...