Browse Prior Art Database

Fault Tolerant Host Channel Adapter

IP.com Disclosure Number: IPCOM000122591D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 120K

Publishing Venue

IBM

Related People

Crandall, D: AUTHOR [+5]

Abstract

This article describes a method and hardware enablement for implementing a fault tolerant attachment between a fault tolerant computer system and another system (host system).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fault Tolerant Host Channel Adapter

      This article describes a method and hardware enablement
for implementing a fault tolerant attachment between a fault tolerant
computer system and another system (host system).

      The attachment disclosed herein appears as a normal fault
tolerant controller to the fault tolerant system and as a standard
control unit to the host system I/O bus.  The appearance to the host
system I/O bus is accomplished by emulating a currently available
control unit.  The emulation is achieved through loadable microcode
which may be altered to emulate a specific control unit type,
executing on the fault tolerant hardware.  Different control unit
emulations are achieved by loading separate emulation code modules.
Errors in the operation of the particular emulation may be corrected
by simply changing the emulation code.

      The fault tolerant attachment of this article is shown in
functional block diagram in the drawing.  It is comprised of the
elements as follows:
-    A BUS TRANSCEIVER - a receiver/buffer and latch/driver which
transfers data to/from one of the fault tolerant system buses from/to
the fault tolerant attachment microprocessor.
-    B BUS TRANSCEIVER - a receiver/buffer and latch/driver which
transfers data to/from one of the fault tolerant system buses from/to
the fault tolerant attachment microprocessor.
-    C BUS TRANSCEIVER - receivers and drivers which pass control
signals and clocks between the fault tolerant system and the fault
tolerant attachment.
-    BUS ARBITRATION - the logic element which requests access to the
fault tolerant system bus, controls the access for the
microprocessor, and provides the bus selection multiplexing in the
event an error is detected on either the A BUS or B BUS.
-    MICROPROCESSOR - a general-purpose computing element which
provides the control, by program execution for the interface between
the fault tolerant system and the fault tolerant attachment
microsequencer.
-    INTERNAL I/O - functional elements such as timer and interrupt
functions used as aids to the microprocessor.
-    MULTI-PORT MEMORY - the storage area common to both the fault
tolerant attachment microprocessor and the microsequencer for storage
of data, control information, and instruction storage for
microprocessor.
-    HOST CHANNEL MICROSEQUENCER - a logic element which acts to
interface the host system I/O bus to the fault tolerant attachment.
-    COMPARATORS - logic which verifies that each "side" of the fault
tolerant attachment is executing the same instructions, passing the
same data, and addressing the same locations.  Should an error occur,
the co...