Browse Prior Art Database

Noise Control for CMOS SRAM Bit Lines

IP.com Disclosure Number: IPCOM000122618D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Carter, EL: AUTHOR [+5]

Abstract

Disclosed is a circuit design technique for controlling the noise which may couple onto the read bit lines of a CMOS static RAM (SRAM). The design consists of adding a brief discharge at the beginning of the SRAM's normal precharge time. This eliminates the exposure to positive coupled noise accumulation on read bit lines that are subject to a high impedance state.

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Noise Control for CMOS SRAM Bit Lines

      Disclosed is a circuit design technique for controlling
the noise which may couple onto the read bit lines of a CMOS static
RAM (SRAM).  The design consists of adding a brief discharge at the
beginning of the SRAM's normal precharge time.  This eliminates the
exposure to positive coupled noise accumulation on read bit lines
that are subject to a high impedance state.

      The figure shows a typical read bit line configuration for a
CMOS SRAM.  The disclosed noise control technique is implemented with
the addition of transistor T4.  Operation is as follows:  During the
initial phase of the array's clock cycle, the bit lines are
precharged by activating T1. In this article, however, activation of
T1 is delayed slightly, and T4 is briefly activated at the beginning
of this precharge time.  This discharges the bit lines of any
positive noise which may have coupled onto them in the previous
cycle.  The associated clock, precharge, and discharge signals are
also depicted in the figure. Conventional delay and clock chopping
circuitry is used to implement the precharge and discharge signals.
After the bit lines are precharged, a standard read access occurs.
If the array cell contains a logical zero, a pull-down device within
the array cell is activated to propagate the zero through the bit
line and sense amp.  If the array cell contains a logical one, the
precharged state is held via the feedback transistor T2.

      The benefit of the disclosed noise control is described as
follows:  After precharging by T1, the read bit line voltage is one
threshold voltage below Vdd, and T3 (used for capacitance isolation)
is virtually off.  Thi...