Browse Prior Art Database

Task Management of Multiple Digital Signal Processors

IP.com Disclosure Number: IPCOM000122619D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 114K

Publishing Venue

IBM

Related People

Cresp, J: AUTHOR [+2]

Abstract

An architecture is disclosed by which multiple slave digital signal processors are managed by the combination of a master digital signal processor and a host computer. The benefit of the architecture comes in signal processing applications with predictable workload, by giving the host computer the option to make high-level task assignment decisions (on the order of seconds), while leaving the master signal processor free to efficiently perform realtime task dispatching and data transfer (on the order of milliseconds).

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Task Management of Multiple Digital Signal Processors

      An architecture is disclosed by which multiple slave
digital signal processors are managed by the combination of a master
digital signal processor and a host computer. The benefit of the
architecture comes in signal processing applications with predictable
workload, by giving the host computer the option to make high-level
task assignment decisions (on the order of seconds), while leaving
the master signal processor free to efficiently perform realtime task
dispatching and data transfer (on the order of milliseconds).

      A sample application that can be implemented using the
architecture is telephone digital voice processing, where the host
computer would control the assignment of telephone channels to slave
signal processors, while the master signal processor would supervise
the discrete and repetitive transfers of voice data to and from the
slave processors.

      The architecture layout is as follows:
      -    A controlling host computer performs high-level system
control, initialization and maintenance of the task allocation table
(described in the following), and post-processing of signal processor
output data. The host computer has access to the resources of the
master signal processor.  The resources in the current implementation
consist of data and instruction memories. In certain simplified
cases, the host computer function could be integrated onto the master
signal processor.
      -    A master signal processor invokes tasks on the slave
signal processors and transfers the raw input and final output data.
The master has access both to its own local resources and to the
resources of all slaves.
      -    Multiple slave signal processors execute tasks. The slave
processors can be considered as hardware subroutines. For cost
savings, the access of slaves can be limited to their private local
resources.

      The architecture is designed for environments where each slave
is responsible for up to "N" tasks, which are invoked sequentially by
the master signal processor during a time-step of fixed-length. The
proportion of each time-step dedicated to a particular task on a
slave is a function of that task's state. The worst-case execution
time of each task state is known, being a function of path-length and
no...