Browse Prior Art Database

High Performance Common Bus for Multi-speed Devices

IP.com Disclosure Number: IPCOM000122639D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Fukuda, M: AUTHOR [+3]

Abstract

Disclosed is a high-performance bus mechanism for a multiprocessor system in which several bus masters access several devices via a shared bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Performance Common Bus for Multi-speed Devices

      Disclosed is a high-performance bus mechanism for a
multiprocessor system in which several bus masters access several
devices via a shared bus.

      In conventional shared-bus multiprocessor systems, when a bus
master reads data from a device, it continues to occupy the shared
bus until its read access is completed. As a result, when a bus
master accesses a low-speed device, other bus masters cannot access
other devices for a long time. For very low-speed devices,  the
interrupt method is used to make efficient use of the bus. For most
microprocessors, interrupt processing takes more than one hundred CPU
cycles. This is several tens of microseconds. Thus, for devices whose
access time is several tens of cycles, the interrupt method is not
very effective. However, some systems have two or more special buses:
one for high-speed devices and one for low-speed devices. In this
case, the system throughput is higher than in a single-bus system,
but the hardware complexity and cost increases markedly. The
disclosed mechanism realizes a high-performance bus that is connected
to several bus masters and several access-speed devices without a
large increase in the cost of hardware. In this mechanism, a bus
master can access low- speed devices without retaining sole
occupation of the shared bus and without using the interrupt method.
Therefore, while a bus master is waiting for the requested data,
other bus masters can access...