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Operating Range Monitor for VLSI Logic

IP.com Disclosure Number: IPCOM000122642D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Sibbers, DE: AUTHOR

Abstract

Operational Integrity of VLSI logic chips can be enhanced by the use of an error detector utilizing on-chip logic delay measurements.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Operating Range Monitor for VLSI Logic

      Operational Integrity of VLSI logic chips can be enhanced
by the use of an error detector utilizing on-chip logic delay
measurements.

      At the wafer, level strings of logic blocks are measured for
delays to determine the quality of the chip-manufacturing process.
This apparatus carries the idea a step further by building a
measurement system on-chip which can continually monitor the delay
characteristics of the chip during functional use.  If the chip's
local environment changes so that the chip's delay characteristics
fall out of the range that it was designed (and analyzed using timing
analysis), then an error indication is asserted.

      The logic provides for determining if the chip is too fast as
well as too slow.  Chips using overlapped clocks may fail if the chip
is too fast.

      The essential hardware elements are:
1.  A delay string made up of logic delay blocks and having 2 delay
taps which represent the limits for slow and fast chips.
2.  A state machine which applies a measurement pulse to the delay
string and determines when to sample the delay string taps.
3.  Detection logic which samples the delay string taps when directed
by the state machine and produces an error indication if an
out-of-range condition is detected.

      Referring to the figure, the Monitor Hardware repeats the
following sequence continuously:
1.  In step with System Clock 7 State Machine 5 asserts a step
function signal to Delay String 1 via Input 2.
2.  After a time referenced to System Clock 7 the State Machine 5
sends a single clock pulse to Detection Logic 6.  The time elapsed
since the beginning of the step function is referred to as the
Measure ment Interval.  Error 8 is the output of a latch within
Detection Logic 6 which is set if either of the following conditions
is true when the single clock pulse is received:
     (A).  Output Slow TP 3 of Delay String 1 is inactive, indicating
that the chip is slower than the design range.
     (B).  Output Fast TP 4 of Delay String 1 is active, indicating
that the chip is faster than the...