Browse Prior Art Database

Single Chip Status Register

IP.com Disclosure Number: IPCOM000122672D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Muerle, U: AUTHOR

Abstract

A part of a computer system is shown which achieves control functions for the overall system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Single Chip Status Register

      A part of a computer system is shown which achieves
control functions for the overall system.

      The control functions are implemented in a programmable logic
called single chip status (SCS) register which is independent of
other system components and connects directly to the system bus and
the select logic.

      The select logic assigns special memory or I/O regions to the
devices provided in the system.

      There are two types of status lines in the SCS:
      1)   output status lines to set and/or to read back logical
states, and
      2)   input status lines which only read logical states caused
by other system components.

      Logical states are set on output status lines to control other
components.  Parity checking, for instance, may be enabled or
disabled by properly setting an output status line.

      The input status lines are used to check the status previously
set by other system components, like watchdogs or parity checkers.

      The SCS appears to the processor as two ports, one of which has
read/write access and the other has read access only.  The first port
houses the output status lines and the second reports the input
status lines.