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Floating Point Vector Microcode Exception Emulation

IP.com Disclosure Number: IPCOM000122701D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Vanover, MT: AUTHOR [+2]

Abstract

The advanced floating-point accelerator of the IBM RT-PC* is controlled by a microcoded sequencer. The horizontal nature of the microcode suggests the possibility of vector functions with a large degree of overlap of the elemental operations comprising such operations.

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Floating Point Vector Microcode Exception Emulation

      The advanced floating-point accelerator of the IBM RT-PC*
is controlled by a microcoded sequencer.  The horizontal nature of
the microcode suggests the possibility of vector functions with a
large degree of overlap of the elemental operations comprising such
operations.

      Related Definitions:
      1) Scalar operation - one set of data for one mathematical
operation.
      2) Vector operation - multiple sets of data for one
mathematical operation.
      3) Compound operation - multiple operations.
      4) Exception - IEEE floating-point exception.  One of overflow,
underflow, invalid operation, divide by zero or inexact result.

      Performance optimization requires maximum overlap. However, the
simultaneous requirement that all operations conform completely to
IEEE Standard 754 poses a serious obstacle, since including microcode
to allow floating-point exception handling to take over at the point
where the exception occurred would be mutually exclusive with the
goal of maximum overlap (see Fig. 1).  That is, the inserted
microcode for the occasional exception would add to execution time,
and any results, temporary or final, scheduled in the microcode,
would be lost if an exceptional branch were taken.

      This was overcome by creating a totally IEEE-conforming self-
emulation routine capable of handling any compound instruction
created from a combination of scalar in...