Browse Prior Art Database

Method of Fabricating a New Merged Stacked Trench Capacitor Memory Cell Structure

IP.com Disclosure Number: IPCOM000122703D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 5 page(s) / 190K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

Disclosed is a new three-dimensional DRAM cell structure and method for fabrication. The cell consists of an access mesa transistor and a merged stacked trench (MST) capacitor and deep trench storage capacitor. The new MST cell is arranged such that a vertical pillar storage capacitor is built in a stacked position over the trench capacitor and the access transistor. The stacked capacitance can be adjusted by controlling the height of the polysilicon pillars. The cell is designed to be built by a fully planarized technology. The stacked capacitor is built after bitline formation. The new cell can be designed using either open bitline or folded bitline architectures without any additional process modifications. The cross section of a unit cell and its layout for the folded bitline architecture are shown in Figs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method of Fabricating a New Merged Stacked Trench Capacitor Memory
Cell Structure

      Disclosed is a new three-dimensional DRAM cell structure
and method for fabrication.  The cell consists of an access mesa
transistor and a merged stacked trench (MST) capacitor and deep
trench storage capacitor.  The new MST cell is arranged such that a
vertical pillar storage capacitor is built in a stacked position over
the trench capacitor and the access transistor.  The stacked
capacitance can be adjusted by controlling the height of the
polysilicon pillars.  The cell is designed to be built by a fully
planarized technology. The stacked capacitor is built after bitline
formation.  The new cell can be designed using either open bitline or
folded bitline architectures without any additional process
modifications.  The cross section of a unit cell and its layout for
the folded bitline architecture are shown in Figs. 1 and 2,
respectively.  The fabrication steps for a p-array MST cell are
described below in two parts:

      The first part of the fabrication process is to complete the
basic mesa transistor trench (MTT) capacitor cell structure.  The
process sequence of the MTT cell is described in (1).  The
fabrication steps begin with trench capacitor formation, then
selective epi growth, patterning mesa area, N-well formation, RIE
poly-Si sidewall spacer, CVD oxide deposition, planarization, STI
formation, transfer gate electrode and wordline formation, junction
formation, and then continues up to the polysilicon planarization
using known MOS process steps, as shown in Fig. 3.  The MTT cell can
be replaced by other similar trench cells as the basic structure
without loss of generality.

      The second part of fabrication processes for the MST cell is to
build a storage capac...