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Single To Multiprocessor Extension Mechanism

IP.com Disclosure Number: IPCOM000122710D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Fukuda, M: AUTHOR [+3]

Abstract

Disclosed is a mechanism for smoothly upgrading existing single-processor to multiprocessor systems. The basic features are (1) to use a processor's bus-holding facility, (2) to add two open-collector buffers and three signals for the communication between the main and the secondary processors, and (3) to adapt an arbiter for more extension.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Single To Multiprocessor Extension Mechanism

      Disclosed is a mechanism for smoothly upgrading existing
single-processor to multiprocessor systems.  The basic features are
(1) to use a processor's bus-holding facility, (2) to add two
open-collector buffers and three signals for the communication
between the main and the secondary processors, and (3) to adapt an
arbiter for more extension.

      Fig. 1 shows a circuit for implementing the mechanism. A single
processor usually has HOLD     and HLDA signals to arbitrate its bus
with a DMA controller in the bus-holding protocol.  Notations such as
HOLD     specifies HOLD     is active low.  The mechanism has two
open-collector buffers #1 and #2 at the output of HOLD     and HLDA#,
respectively.  Three signals from the main processor go to the
secondary one's multiprocessor extension logic.  They are (1) an
output of the buffer #1 (HOLD#), (2) an output of the buffer #2
(BHLDA#), and (3) HLDA.  They give no effect to the single-processor
configuration.

      The following is a bus arbitration protocol between two
processors by using this mechanism.  The main processor is granted to
use the bus unless it receives a hold request. When the secondary
processor requests the bus, the multiprocessor extension logic sees
if HOLD     is inactive. If HOLD     is inactive, then HOLD     is
asserted in order to have the main processor release the bus.  At the
same time, this extension logic drops BHLDA to prevent a DMA
controller from receiving an active BHLDA.  The exte...