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Producing Operation Codes for a Parallel Architected Processor

IP.com Disclosure Number: IPCOM000122744D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 56K

Publishing Venue

IBM

Related People

Mitchell, NA: AUTHOR [+2]

Abstract

Disclosed is a method for producing machine operation codes for a parallel architected processor from a free format assembly language. Individual operations of compound instructions are separately assembled into operation codes which are used to form the required operation code.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 66% of the total text.

Producing Operation Codes for a Parallel Architected Processor

      Disclosed is a method for producing machine operation codes for
a parallel architected processor from a free format assembly
language.  Individual operations of compound instructions are
separately assembled into operation codes which are used to form the
required operation code.

      When assembly language programmers are allowed to use free
format coding techniques when coding for parallel architected
processors, it becomes necessary to distinguish between instructions
which are singular operations and instructions which are compound
operations.  By assembling all instructions as singular operations,
an assembler may collect all of the information that is needed to
produce any compound operation codes which are required.

      When the assembly language's free format syntax indicates that
an instruction is a singular operation, the operation code which was
generated is produced for the instruction.  When the syntax indicates
that an instruction is a compound operation, the assembler checks the
singular operation codes which were generated for compound operation
restrictions.  When no compound operation restrictions are violated,
the assembler produces the required compound operation code for the
instruction.

      An Example:  Consider a processor that has 6 registers, one
adder, and one subtracter.  The possible instructions and operation
codes are:
1.   a = b + c      ...