Browse Prior Art Database

Improved Wet Etch Process for Gate Oxide Stripping

IP.com Disclosure Number: IPCOM000122797D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Chanclou, R: AUTHOR [+4]

Abstract

Disclosed is a wet etch process designed to reduce Gate Conductor (GC) to Deep Trench (DT) shorts and Long Retention Time (LRT) fails in 16-Mbit DRAM chips (could cover also the 256-Mbit DRAM chips and follow-on products).

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Improved Wet Etch Process for Gate Oxide Stripping

      Disclosed is a wet etch process designed to reduce Gate
Conductor (GC) to Deep Trench (DT) shorts and Long Retention Time
(LRT) fails in 16-Mbit DRAM chips (could cover also the 256-Mbit DRAM
chips and follow-on products).

      A state of the art etchant is Diluted HydroFluoric acid
(DHF).  This etchant removes silicon oxide faster than nitride so
that node nitride remainings, so called "nitride horns" are left in
the course  of the GC stack fabrication.  They are visible after
sacrificial gate oxide layer removal around the deep trench, as
depicted in the attached  drawing.

Such "nitride horns" create two types of defects:
  1.  GC polysilicon remainings under "nitride horns" along DTs,
       so that when GC dry etch time is too short, GC to DT shorts
       are produced.
  2.  Node nitride remainings charging when GC dry etch time is
       too long (gate oxide layer damage) which results in Long
       Retention Time (LRT) fails.

      The wet process can be significantly improved by the chemistry
disclosed herein, which uses a mix of hydrofluoric acid and glycerol
(or a product like ethylene glycol).  This chemistry etch SiO2 and
Si3N4 at approximately the same rate (thermal SiO2:Teos SiO2:Si3N4
ratio is 1:1.10:1.15).

      As a consequence, "nitride horns" are substantially eliminated,
thereby reducing drastically GC to DT short and charging effects.  In
addi...