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Browse Prior Art Database

Peripheral Component Interconnect Sideband Signals on Expansion Slots

IP.com Disclosure Number: IPCOM000122854D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Journey, J: AUTHOR [+3]

Abstract

Disclosed is a method for degating wait states during a Peripheral Component Interconnect (PCI) Bus data transfer. This method involves the design and implementation of a specific type of signal known as a PCI sideband signal.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Peripheral Component Interconnect Sideband Signals on Expansion Slots

      Disclosed is a method for degating wait states during a
Peripheral Component Interconnect (PCI) Bus data transfer.  This
method involves the design and implementation of a specific type of
signal known as a PCI sideband signal.

      The Xilinx PCI Logicore design, as delivered, inserts wait
states whenever it is the source of data that is transferred over the
PCI bus.  This wait state insertion degrades the PCI Bus bandwidth
performance to half of its maximum during burst transfers.  A method
to degate these wait states was developed using what is called
sideband signals.  The PCI Bus defines a sideband signal as a "signal
that is not  part of the PCI bus standard and interconnects two or
more PCI agents.  This signal only has meaning for the agents it
interconnects."

      The design uses what is called a "Fast Mode" cable to connect
the two agents.  This two conductor cable connects a Initiator PCI
agent to a Target PCI agent.  During a PCI burst data transfer where
the Initiator agent is sourcing data from the Target agent, this
signal is asserted and causes the Target agent's state machine logic
to supply data on every rising clock edge during the data cycle of
the PCI burst data transfer.  This behavior is consistent with
degating the wait states and allows full PCI bandwidth operation
during this specific data transfer case.