Browse Prior Art Database

Method for Fabricating Self-Aligned Thin-Film Transistors

IP.com Disclosure Number: IPCOM000122863D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Miyamoto, T: AUTHOR

Abstract

Disclosed is a method for fabricating Thin Film Transistors (TFT) of inverted-staggered type with source and drain electrodes self-aligned to gate electrode. The TFT structure with self-aligned source/drain electrodes reduces a variation of parasitic capacitance between the gate and the source/drain electrodes and enables scaling down of the channel dimensions. In this fabricating method, a backside exposure method with negative-type photoresist coated on an ohmic contact layer, which is formed with low resistivity material, is used in order to define the source/drain electrodes.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 74% of the total text.

Method for Fabricating Self-Aligned Thin-Film Transistors

      Disclosed is a method for fabricating Thin Film Transistors
(TFT) of inverted-staggered type with source and drain electrodes
self-aligned to gate electrode.  The TFT structure with self-aligned
source/drain electrodes reduces a variation of parasitic capacitance
between the gate and the source/drain electrodes and enables scaling
down of the channel dimensions.  In this fabricating method, a
backside exposure method with negative-type photoresist coated on an
ohmic contact  layer, which is formed with low resistivity material,
is used in order  to define the source/drain electrodes.

      The Figure shows the fabricating process of the
channel-passivated inverted-staggered self-aligned TFT.  A gate
electrode (1), of which material is opaque due to the backside
exposure method, is formed on a transparent substrate (Fig. 1a).
Gate insulator layer ((2) e.g., SiOx), channel layer ((3) e.g.,
amorphous silicon), and channel passivation layer ((4) e.g., SiNx)
are deposited.  The self-aligned channel-passivation (4) is patterned
on the gate electrode by backside exposure method of positive-type
photoresist (Fig. 1b).  An ohmic contact layer (5) is deposited
(Fig. 1c).  The layer is formed with transparent material because
self-aligned source/drain electrodes are patterned by using
negative-type photoresist (6) exposed from backside (Fig. 1d).  The
material also has low-resistivity because the source/...