Browse Prior Art Database

Self Optimization of Working Frequency for Computer Subsystems

IP.com Disclosure Number: IPCOM000122876D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 17K

Publishing Venue

IBM

Related People

Daniels, LS: AUTHOR [+2]

Abstract

Disclosed is a method of heuristic self-optimization of busses' and chips' operating frequencies in a general nature computer system. The method helps to "extract" additional system performance hidden due to inevitable conservatism of technology specifications and conservatism/imprecision of timing/noise analysis tools.

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This is the abbreviated version, containing approximately 43% of the total text.

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Self Optimization of Working Frequency for Computer Subsystems

Disclosed is a method of heuristic self-optimization of busses' and chips' operating frequencies in a general nature computer system. The method helps to "extract" additional system performance hidden due to inevitable conservatism of technology specifications and conservatism/imprecision of timing/noise analysis tools.

System busses (Input/Output (I/O) and Central Electronic Complex (CEC) busses) are becoming progressively more a system performance bottleneck, as the processor chips speed goes up. One of the ways to increase bus performance is to raise its operating frequency. However, due to a large number and complexity of components involved, the supported overall performance for each of the system busses is typically limited to the low end of their potential capacity. This disclosure addresses two of the reasons for this minimum performance design point. 1. The development tools used to simulate and evaluate the

design parameters have a certain inherent inaccuracy.

They are models, not the real thing. Therefore, system

operating frequencies must be reduced a certain amount to

guarantee that any modeling errors are overcome.

2. Each of the several silicon chips involved in the realization

of a design has its own guaranteed operating speed. This

specified speed is a minimum number that takes into account

all of the manufacturing process and packaging variations.

While this minimum number must be used to fix the speed at

which the system is guaranteed to operate, the reality is

that the likelihood of any one chip exhibiting the worst

case on all the process and packaging variations is

relatively small. The vast majority of components will

operate at speed faster than the guaranteed specification.

This is particularly true of custom ASIC designs where a

single customer is obligated to accept the whole lot,

rather than sorting the lot into several price ranges

for a variety of customers.

The subject of this disclosure describes a mechanism by which the above process and nominal design variations for a given system can be determined after the system has been assembled. A timing control mechanism could then be set to allow the system to operate at its maximum speed system rather then the guaranteed speed for all systems.

The product design includes a configurable clock frequency circuit for each of the performance critical subsystems (bus, memory interface, etc.) and a mechanism to set the frequency via program control. In addition, a procedure to test the operation of the critical subsystem under stress, determine the maximum safe value and set the clock to maximum value would be defined.

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The dynamically adjustable clock frequency can be implemented by using currently available technology. Phase-lock loop clock circuits provide an inexpensive means for clock control over a range of frequencies. The control element can be digitally accessed. This is an impo...