Browse Prior Art Database

Flexible Transfer Size Dependent Data Buffering Scheme in a Symmetric Multiprocessor

IP.com Disclosure Number: IPCOM000122895D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Maule, W: AUTHOR [+2]

Abstract

Disclosed is a method of efficiently using a fixed size data buffer pool in a memory controller. The design supports different processors with different cache line sizes, as well as provides efficient use of the buffer pool, for small transfers (i.e., much less than the size of the system cache line).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Flexible Transfer Size Dependent Data Buffering Scheme in a Symmetric
Multiprocessor

      Disclosed is a method of efficiently using a fixed size data
buffer pool in a memory controller.  The design supports different
processors with different cache line sizes, as well as provides
efficient use of the buffer pool, for small transfers (i.e., much
less than the size of the system cache line).

      The memory controller described incorporates a buffer scheme
that makes efficient use of its internal data buffering.  The
discussion will concentrate on the buffering scheme that buffers data
from the processor targeted to either memory or Input/Output (I/O).
A similar buffer scheme is used to source data from memory and from
I/O as well.  Several terms used pervasively throughout the
discussion will be defined.  A "beat" of data is the equivalent of
the amount of data transferred across a bus in one bus cycle.  A
"cache line" is the amount of data that is equal to the coherency
size of the system.  In the system described, there are two cache
line sizes supported, in order that the memory controller might be
used for two distinct processor design points (provided that in an
multi-processor system, a homogeneous set of processors is used).
The two cache line sizes supported are the equivalent of four beats
and eight beats.

Fig. 1 shows a possible system topology that utilizes the memory
controller described.  Processors 1-N must have a common cache line
size.  The memory controller is programmable to support either of two
cache line sizes.  Processors write data to memory or I/O.  On
average, most processor writes to memory will be equal in length to
the cache line size.  The memory is programmable to support burst
transfers (without gaps) of either cache line size supported.
Processor writes to I/O are often less than the cache line size
(potentially one beat of data).  It is clear, given the variability
of transfer sizes and cache line size configurations that some
flexibility in the data buffer  management design is needed to obtain
efficient use of the data buffer.

      Fig. 2 shows the buffer used to hold data received from the...