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Browse Prior Art Database

Vertical Memory Redundancy Using Standard Commercial Modules

IP.com Disclosure Number: IPCOM000122905D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 145K

Publishing Venue

IBM

Related People

Carnevale, MJ: AUTHOR [+3]

Abstract

Disclosed is a method for storing Error Correction Codes (ECC) in standard width memory modules.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Vertical Memory Redundancy Using Standard Commercial Modules

      Disclosed is a method for storing Error Correction Codes (ECC)
in standard width memory modules.

      Memory modules like dynamic Random Access Memory (DRAM), Static
Random Access Memory (SRAM), Electrically Erasable Programmable Read
Only Memory (EEPROMs), or an EEPROM that can be updated by diskette
(FLASH) all experience soft errors and hard failures.  Most hard
failures and virtually all soft errors are single bit failures.
Standard ECC algorithms will correct these errors, but those
algorithms require the  memory modules to be arranged in 22-bit,
39-bit, 40-bit or 80-bit words.  Most current memory chips are x4,
x8, x16 bit devices. Standard  implementations of Error Correction
Codes (ECC) require the use of extra  memory modules, wider data
busses, and unconventional non-standard memory  configurations.

      One method to get around some of the drawbacks mentioned above
is to store the ECC vertically in the memory module.  This allows
full ECC support on a single xMx8 FLASH chip, or on a standard xMx32
DRAM Single In-line Memory Module (SIMM).  This function can be
enabled or disabled when the application chooses.  Because of the
addressing scheme,  DRAM must be reloaded after enabling or disabling
ECC; FLASH does not need to be reloaded.

      New memory modules are becoming very large; 2M-byte DRAMs and
FLASH chips are standard, 8M-byte DRAM chips are available now.
Also, the data transfer rates the modules support is increasing.
Currently FLASH memory on microprocessors consists of a single
unprotected x8 or  x16 memory module and most Personal Computer (PC)
system memories consists of XMx32 memory SIMMs.  There are two main
parts that will be  discussed here; one allows ECC protection on x8
memory, the other part  allows ECC protection using x32 memory.  This
enables the use of ECC on  the standard memories used by most of the
computer industry.

      Current FLASH or Read-Only Storage (ROS) chips are quite
large, up to 2M-bytes or more, so only one may be required for an
application.  Using three or five FLASH modules to get a 22-bit or
40-bit ECC word is an unacceptable option because of cost, card real
estate, and the extra failure rate of having two to four more parts.
Memory increases by 2x jumps; for example, 512Kx8, 1Mx8, 2Mx8 are
standard FLASH chips.  Since code may not require the full space in a
FLASH, it is reasonable to assume this can be used for ECC.  Storing
ECC vertically will use 1/5 of the FLASH to store the ECC.  This
allows full ECC protection on the FLASH at no cost increase and with
the use of a single standard FLASH module.  Today the vendor wrld
does not use any protection on most FLASH applications because they
cannot justify the extra cost and card real-estate associated with
ECC, in fact most do not even use parity on these modules.  With this
method, those applications could gain full ECC p...