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Leakage Current Reduction/Minimization through Substrate and/or Well Bias Control Coupled with Clock Power Management

IP.com Disclosure Number: IPCOM000122923D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Correale Jr, A: AUTHOR

Abstract

Leakage currents associated with off transistors have not been a major problem in the recent past. However, with the advent of reduced power supply voltages and corresponding reduced device threshold voltages to improve performance, coupled with the increased density which allows ever more devices to be fabricated on a single chip, the leakage current associated with off-devices is now an issue. This is especially a problem in low power devices/products. Clock power management schemes have been employed to reduce power when the device is not active and/or when only when subsections of complex devices need to be active. Timers coupled with Clock Power Management (CPM) circuits de-activate the clocks after periods of inactivity.

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Leakage Current Reduction/Minimization through Substrate and/or Well
Bias Control Coupled with Clock Power Management

      Leakage currents associated with off transistors have not been
a major problem in the recent past.  However, with the advent of
reduced power supply voltages and corresponding reduced device
threshold voltages  to improve performance, coupled with the
increased density which allows  ever more devices to be fabricated on
a single chip, the leakage current  associated with off-devices is
now an issue.  This is especially a problem in low power
devices/products.  Clock power management schemes  have been employed
to reduce power when the device is not active and/or  when only when
subsections of complex devices need to be active. Timers  coupled
with Clock Power Management (CPM) circuits de-activate the clocks
after periods of inactivity.  All these techniques have the single
goal of minimizing the power dissipation of a device to improve
battery life  and thermal issues.  This power reduction, however,
will be compromised  if the "off-state" leakage current of a powered
device with inactive clocks is not controlled.

      Disclosed is a method which will address a technique wherein
the clock power management circuitry coupled with on-chip substrate
and/or well bias circuits can effectively control the off-state
leakage without any degradation in operational performance or ability
to sort high performance products.  Described is a method wherein
stand-by or static leakage power can be minimized without degrading
functional performance or reducing the ability to sort premium high
performance product.  This scheme does not require appreciable
silicon area to implement.  The implementation can also include a
means to instruct the  clock power management unit to delay
reactivation from sleep modes or return from sleep modes with a
reduced clock frequency until the appropriate back-bias is obtained.
This bi-directional communication between the clock power management
unit and the bias generators can result in optimal performance while
minimizing stand-by or off-current  leakage.

      Substrate or bulk bias generators have been used in the past to
control threshold voltages of transistors for performance (*).  These
bias generators are often process compensated in an attempt to
control the generated voltage over a spread of applied power supply
voltage, temperature and process variations.  They seek to narrow the
distributions or variations in the perform of a device by controlling
the threshold voltages.  This narrowing of the performance
distributions can be detrimental in obtaining higher performance
products by sorting  the product.  These higher performance sorted
products often carry a high  price and, hence, profit, making them
highly desirable.  On the other side of this spectrum, the lower
power dissipating product may also carry a premium.  Hence, on-chip
bias generators, while...