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Static Evaluate Technique for Domino Circuitry

IP.com Disclosure Number: IPCOM000122952D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 106K

Publishing Venue

IBM

Related People

Durham, CM: AUTHOR [+2]

Abstract

A new method that allows domino circuitry to operate in a slow, static mode is presented. Known (in general) as "static evaluate", this method requires no additional devices in the domino circuits by utilizing the clock devices for the operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Static Evaluate Technique for Domino Circuitry

      A new method that allows domino circuitry to operate in a slow,
static mode is presented.  Known (in general) as "static evaluate",
this method requires no additional devices in the domino circuits by
utilizing the clock devices for the operation.

      As processors have continually increased speed requirements,
designers have turned to more complex circuit structures to keep up
with demands.  One such circuit style is known as "domino", which is
a type  of dynamic circuit.  As shown in Fig. 1, domino circuits
consist of a "Domino Logic Block", an nmos and pmos device pair
connected to the "Clock" signal, and output inverter (an mnos and
pmos pair), and a feedback pmos device.

      A standard domino circuit uses the "Logic Inputs" and "Clock"
signals to produce the "Out" signal.  Because of the inherent dynamic
characteristic of the circuit, this function requires two distinct
phases of operations: "precharge" and "evaluate".  The "precharge"
phase sets  the domino circuit to a known state while "Clock" is low,
which forces  "Out" low.  The "evaluate" phase permits the domino
circuit to selectively switch "Out" based on the "Logic Inputs".
This causes "Out" to go high if both the inputs and the "Domino Logic
Block" so determine.  Note that the domino circuit cannot return to
the precharged  state without a precharge phase occurring.  Thus, any
false switching during the evaluate phase is non-recoverable and will
cause a logical failure.  Under normal operation, the domino circuit
is designed so as  to eliminate such events from such effects as
noise on the logic inputs  and parasitic leakage through the nmos
devices in the logic block (which  can cause a loss of the precharged
state).  These problems are amplified  under reliability screening
procedures.

      One common reliability screen is "Burn-In" where, typically,
the supply rail is elevated to 1.5 times the normal value, the
temperature is raised to 140C, and the operational speed is reduced
to less than .10 MHZ.  These changes have several effects: (1)
increases the  noise coupling on the input signals by 1.5x; (2)
reduces the threshold of  the nmos evaluation devices, which reduces
the inherent noise margin; (3)  increases the leakage through the
nmos devices, possibly above the amount  to be supplied by the pmos
feedback device, which means the precharge state may be lost; (4)
reduces the current drive through the feedback pmos...